Rapidly-readable register file

• US 6,219,756 B1
• Filed: 08/11/1998
• Issued: 04/17/2001
• Est. Priority Date: 12/24/1997
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kasamizugami, Masayoshi
• Primary Examiner(s): Pan, Daniel H.
• Assistant Examiner(s): CHEN, TE Y
• Application Number:
  US09/132,314
• Time in Patent Office: 980 Days
• Field of Search: 365/230.05, 365/189.02, 711/127, 327/57, 307/38, 712/300, 712/22, 712/218
• US Class Current: 711/127
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

The present invention discloses a register file in which a read access time is reduced, a data bus width is made expandable, more rapid decoding can be given at a time of data readout, and the whole logic unit is made higher in performance. For these purposes, in the register file of the invention, register arrays are classified into a plurality of banks, and a sense amplifier is provided for each of the banks. Further, the register file includes a decoder to select a word corresponding to a result of decoding of partial bits of a read address so as to read the word from the register array in each of the banks, a decoder to specify a bank corresponding to a result of decoding of remaining bits of the read address, and a multiplexer to select the word from the bank specified by the decoder so as to output the word to the read port. The present invention can be applied to a storage portion mounted in a processing unit such as microprocessor or CPU to contain intermediate results of a calculation, constants, and so forth.

Claims

1. Addressing circuitry for a register file having a plurality of register arrays, and having a multiport configuration in which a read port and a write port are mounted, and a plurality of read accesses and a plurality of write accesses independently and concurrently are made through the ports, wherein the plurality of register arrays are classified into a plurality of banks every predetermined number of words, and the plurality of banks being respectively provided with a sense amplifier, said addressing circuitry comprising:

an in-bank word selecting decoder, directly connected to each one of the plural banks, to decode partial bits of an address for specifying a word to be read, and select a word corresponding to a result of decoding so as to read the word from the register array in each of the banks;

a bank selecting decoder to decode remaining bits of the address so as to specify the bank corresponding to a result of decoding; and

a multiplexer to take the word selected by the in-bank selecting decoder and amplified by the sense amplifier from each of the plurality of banks, and select a word from the bank specified by the bank selecting decoder from among the words input by the number of banks so as to output the word to the read port.

2. Addressing circuitry for a register file having a plurality of register arrays, and having a multiport configuration in which a read port and a write port are mounted, and a plurality of read accesses and a plurality of write accesses independently and concurrently are made through the ports, wherein the plurality of register arrays are classified into a plurality of banks every predetermined number of words, and the plurality of banks being respectively provided with a sense amplifier, and said addressing circuitry comprising:

an in-bank word selecting decoder, shared among the plural banks, to decode partial bits of an address for specifying a word to be read, and select a word corresponding to a result of decoding so as to read the word from the register array in each of the banks;

a bank selecting decoder to decode remaining bits of the address so as to specify a bank corresponding to a result of decoding; and

a multiplexer to take the word selected by the in-bank selecting decoder and amplified by the sense amplifier from each of the plurality of banks, and select the word from the bank specified by the bank selecting decoder from among the words input by the number of banks so as to output the word to the read port.

3. An addressing circuitry according to claim 2, further comprising:

a first inverter to invert/amplify a signal from the in-bank word selecting decoder; and

a second inverter mounted for each of the banks to invert/amplify a signal from the first inverter, and place the signal on a decode line.

5. An addressing circuitry according to claim 2, wherein there is mounted a bypass line through which a word input from the write port is directly output to the read port, and

the multiplexer having the function as a bypass selecting circuit to select the word through the bypass line, and output the word to the read port.

6. An addressing circuitry file according to claim 3, wherein there is mounted a bypass line through which a word input from the write port is directly output to the read port, and

the multiplexer having the function as a bypass selecting circuit to select the word through the bypass line, and output the word to the read port.

8. An addressing circuitry according to claim 5, further comprising a bypass control circuit to cause the multiplexer to function as the bypass selecting circuit when a read address matches a write address.

9. An addressing circuitry according to claim 6, further comprising a bypass control circuit to cause the multiplexer to function as the bypass selecting circuit when a read address matches a write address.

4. A register file, comprising

a plurality of register arrays having a multiport configuration in which a read port and a write port are mounted and a plurality of read accesses and a plurality of write accesses independently and concurrently are made through the ports, the plurality of register arrays being classified into a plurality of banks every predetermined number of words;

sense amplifiers respectively provided for the plurality of banks;

an in-bank word selecting decoder to decode partial bits of an address specifying a first word to be read, and to select a word corresponding to a result of decoding so as to read the word from the register array in each of the banks;

a bank selecting decoder to decode remaining bits of the address so as to specify a bank corresponding to a result of decoding;

a multiplexer, coupled to the banks and to the bank selecting decoder, to take the word selected by the in-bank selecting decoder and amplified by the sense amplifier from each of the plurality of banks, and to select the first word from the bank specified by the bank selecting decoder from among the words input by the number of banks so as to output the first word to the read port; and

a bypass line coupled to the multiplexer and through which a second word input from the write port is directly output to the read port, and the multiplexer also operates to function as a bypass selecting circuit to select the second word through the bypass line and to output the second word to the read port.

7. A register file according to claim 4, further comprising a bypass control circuit to cause the multiplexer to function as the bypass selecting circuit when a read address matches a write address.

10. A register file, comprising

register arrays having a multiport configuration in which a read port and a write port are mounted and read accesses and write accesses independently and concurrently are made through the ports, the register arrays being classified into banks every predetermined number of words;

sense amplifiers respectively provided for the banks;

an in-bank word selecting decoder, directly connected to each bank, to decode partial bits of an address specifying a word to be read, and to select a word corresponding to a result of decoding so as to read the word from the register array in each of the banks;

a bank selecting decoder to decode remaining bits of the address so as to specify a bank corresponding to a result of decoding; and

a multiplexer, coupled to the banks and to the bank selecting decoder, to take the word selected by the in-bank selecting decoder and amplified by the sense amplifier from each bank, and to select a word from the bank specified by the bank selecting decoder from among the words input by the banks and output the word to the read port.