System and method of retiring misaligned write operands from a write buffer

• US 6,219,773 B1
• Filed: 10/18/1993
• Issued: 04/17/2001
• Est. Priority Date: 10/18/1993
• Status: Expired due to Term

• Current Assignee: VIA-Cyrix, Inc.
• Original Assignee: VIA-Cyrix, Inc.
• Inventors: Garibay, Raul A. Jr., Quattromani, Marc A.
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US08/138,790
• Time in Patent Office: 2,738 Days
• Field of Search: 345/400, 345/425
• US Class Current: 711/201
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags

Abstract

A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads form memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

Claims

1. A microprocessor having a data path of predetermined length that defines a memory block boundary, comprising:

(a) core means for executing a plurality of write instructions to produce a plurality of write operands, each write operand including a data field and an address field;

(b) misalignment control means, coupled to the core means, for indicating if any of the address fields of the plurality of write operands are misaligned with respect to the memory block boundary;

(c) write buffer means having a plurality of entries, coupled to the core means and the misalignment control means, for temporarily storing the plurality of write operands and responsive to the misalignment control means indicating a misaligned write operand, for allocating a first and a second write buffer entry, wherein the address field of the first write buffer entry contains a beginning address in a first memory block for the misaligned write operand and the address field of the second write buffer entry contains a continuation address in a second memory block for the misaligned write operand; and

,

(d) memory means having a plurality of data field entries, coupled to the write buffer means, for storing the data fields of the plurality of write operands.

2. The microprocessor of claim 1 further comprising (e) aligner means, coupled between the data field of the first write buffer entry and a first and a second data field entry in the memory means, for aligning data to the beginning and continuation addresses, respectively.

3. The microprocessor of claim 1 wherein the memory means is a cache memory.

4. The microprocessor of claim 1 wherein each of the plurality of write instructions in (a) includes an operand size and the misalignment control means (b) indicates if any of the plurality of write operands are misaligned by adding the operand size to the beginning address of each write operand to form a sum, and determining whether a carry occurs into an N^th bit of the sum, wherein 2^N defines a width of the data path in bytes.

5. The microprocessor of claim 1 wherein the continuation address of a misaligned write operand in (c) in the second memory block is calculated by adding the operand size to the beginning address in the first memory block and setting N least significant bits to zero, wherein 2^N defines a width of the data path in bytes.

6. A microprocessor having a data path of predetermined length that defines a memory block boundary, comprising:

(a) a core for executing a plurality of write instructions to produce a plurality of write operands, each write operand including a data field and an address field;

(b) misalignment control circuitry, coupled to the core, to indicate if any of the address fields of plurality of write operands are misaligned with respect to the memory block boundary;

(c) a write buffer having a plurality of entries, coupled to the core and the misalignment control circuitry, to temporarily store the plurality of write operands and responsive to the misalignment control circuitry indicating a misaligned write operand, allocating a first and a second write buffer entry, wherein the address field of the first write buffer entry contains a beginning address in a first memory block for the misaligned write operand and the address field of the second write buffer entry contains a continuation address in a second memory block; and

,

(d) memory having a plurality of data field entries coupled to the write buffer.

7. The microprocessor of claim 6 further comprising (e) an aligner coupled between the data field of the first write buffer entry and a first and a second data field in the memory, to align data to the beginning and the continuation addresses, respectively.

8. The microprocessor of claim 7 wherein the memory is a cache memory.

9. The microprocessor of claim 6 wherein each of the plurality of write instructions in (a) includes an operand size and the misalignment control circuitry (b) indicates if any of the plurality of write operands are misaligned by adding the operand size to the beginning address of each write operand to form a sum, and determining whether a carry occurs into an N^th bit of the sum, wherein 2^N defines a width of the data path in bytes.

10. The microprocessor of claim 6 wherein the continuation address of a misaligned write operand in (c) in the second memory block is calculated by adding the operand size to the beginning address in the first memory block and setting N least significant bits to zero, wherein 2^N defines a width of the data path in bytes.

11. In a microprocessor having a core, a data path having a width of N bytes, a write buffer with a plurality of entries, and a memory, a method of retiring misaligned write operands from the write buffer to the memory comprising the steps of:

(a) executing a plurality of write instructions to produce a plurality of write operands, each write operand including a data field and an address field;

(b) indicating if any of the address fields of the plurality of write operands are misaligned with respect to the memory block boundary;

(c) responsive to step (b), allocating a first and a second write buffer entry, wherein the address field of the first write buffer entry contains a beginning address in a first memory block for the misaligned write operand and the address field of the second write buffer entry contains a continuation address in a second memory block; and

,

(d) storing the plurality of write operands to memory.

12. The method of claim 11 further comprising step (e) aligning data from the data field of the first write buffer entry to the beginning and the continuation addresses in the memory, respectively.

13. The method of claim 11 wherein step (b) comprises the steps of:

(i) adding an operand size to the beginning address of each write operand to form a sum; and

,

(ii) determining whether a carry occurs into an Nth bit of the sum, wherein 2^N defines a width of the data path in bytes.

14. The method of claim 11 wherein the continuation address of a misaligned write operand in step (c) is calculating by adding the operand size to the beginning address of the misaligned write operand to form a sum and setting N least significant bits to zero.