Microcontroller with selectable oscillator source

• US 6,219,797 B1
• Filed: 01/14/1998
• Issued: 04/17/2001
• Est. Priority Date: 02/09/1993
• Status: Expired due to Fees

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Grider, Steve, Adams, Matt, Liu, Shyun, Little, Wendell
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US09/007,263
• Time in Patent Office: 1,189 Days
• Field of Search: 713/500, 713/600, 713/322, 713/601, 712/1
• US Class Current: 713/500
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

An 8051 microprocessor core having an ability to operate via an external crystal oscillator or be switched to operate in a low power mode via an internal ring oscillator.

Claims

1. A microprocessor circuit comprising:

a microprocessor core;

a first oscillator circuit for outputting a first signal, said first oscillator circuit configurable in a powered-up state and a powered-down state;

a second oscillator circuit for outputting a second signal;

a switch connected to the first oscillator circuit and the second oscillator circuit, the switch for receiving the first signal and the second signal, and the switch further for outputting an operating clock signal to the microprocessor core, wherein the operating clock signal is generated responsive to one of the first signal and the second signal; and

means for selectively powering-down said first oscillator circuit, thereby reducing power consumption by the first oscillator circuit and placing the first oscillator in the powered-down state;

wherein said microprocessor core is configured to operate according to the operating clock signal generated responsive to the second signal when the first oscillator circuit is in the powered-down state.

2. The microprocessor circuit of claim 1, further comprising:

means for selectively powering-up said first oscillator circuit, thereby bringing the first oscillator circuit from the powered-down state to the powered-up state;

wherein said microprocessor core is configured to operate according to the operating clock signal generate responsive to the first signal when the first oscillator circuit is powered-up.

3. The microprocessor circuit of claim 1, wherein the first oscillator circuit is an external oscillator circuit.

4. The microprocessor circuit of claim 3, wherein the second oscillator circuit is an internal ring oscillator circuit.

5. The microprocessor circuit of claim 1, further comprising:

a divide-by circuit connected to the switch, the divide-by circuit configured to divide one of the first signal and the second signal to thereby generate the operating clock signal.

6. A microprocessor circuit comprising:

a microprocessor core;

a first oscillator circuit for outputting a first signal, the first oscillator circuit configured to be in one of a powered-down state and a powered-up state;

a second oscillator circuit for outputting a second signal;

a switch connected to the first oscillator circuit and the second oscillator circuit, the switch for receiving the first signal and the second signal, and the switch further for outputting an operating clock signal to the microprocessor core, wherein the operating clock signal is produced from one of the first signal and the second signal; and

means for selectively powering-up said first oscillator circuit, thereby bringing the first oscillator circuit from the powered-down state to the powered-up state;

wherein said microprocessor core is configured to operate according to the operating clock signal generated responsive to the first signal when the first oscillator circuit is powered-up.

7. The microprocessor circuit of claim 6, further comprising:

means for selectively powering-down said first oscillator circuit, thereby bringing the first oscillator circuit from the powered-up state to the powered-down state;

wherein said microprocessor core is configured to operate according to the operating clock signal generated responsive to the second signal when the first oscillator circuit is powered-down.

8. The microprocessor circuit of claim 7, wherein the means for selectively powering-down is configured to power-down said first oscillator through a controlled power-down.

9. The microprocessor circuit of claim 6, wherein the first oscillator circuit is an external oscillator circuit.

10. The microprocessor circuit of claim 9, wherein the second oscillator circuit is an internal ring oscillator circuit.

11. The microprocessor circuit of claim 6, further comprising:

a divide-by circuit connected to the switch, the divide-by circuit configured to divide one of the first signal and the second signal to thereby generate the operating clock signal.