Method of manufacturing an insulated trench gate semiconductor device

• US 6,221,721 B1
• Filed: 01/18/2000
• Issued: 04/24/2001
• Est. Priority Date: 03/12/1996
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Thompson, Craig
• Application Number:
  US09/484,256
• Time in Patent Office: 462 Days
• Field of Search: 438/270, 438/260, 438/197, 438/271
• US Class Current: 438/270
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

It is an object to compatibly realize a decrease in an on-state voltage and an increase in a current capable of turn-off. An N layer (43) having an impurity concentration higher than that of an N⁻ layer (42) is formed between the N⁻ layer (42) and a P base layer (44). In the exposed surface of the P base layer (44) connected to an emitter electrode (51), a P⁺ layer (91) having an impurity concentration higher than that of the P base layer (44) is formed. The formation of the N layer (43) allows the carrier distribution in the N⁻ layer (42) to be close to the carrier distribution of a diode, so that the on-state voltage is decreased while maintaining high the current value capable of turn-off. Furthermore, the P⁺ layer (91) allows holes to easily go through form the P base layer (44) to the emitter electrode (51), which increases the current value capable of turn-off.

Claims

1. A method of manufacturing an insulated gate semiconductor device, comprising:

a substrate forming step of forming a semiconductor substrate defining first and second main surfaces and having a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, said first semiconductor layer being exposed in said first main surface and said second semiconductor layer being exposed in said second main surface;

a first implantation step of implanting and diffusing an impurity of the second conductivity type into said second main surface of said semiconductor substrate to an impurity concentration higher than the impurity concentration of said second semiconductor layer to form a third semiconductor layer of the second conductivity type in a surface portion of said second semiconductor layer;

a second implantation step of implanting and diffusing an impurity of the first conductivity type into a surface of said third semiconductor layer to form a fourth semiconductor layer of the first conductivity type in a surface portion of said third semiconductor layer, wherein said third semiconductor layer is so formed as to be thinner after forming said fourth semiconductor layer than said second semiconductor layer remaining;

a third implantation step of selectively implanting and diffusing an impurity of the second conductivity type in a surface of said fourth semiconductor layer to selectively form a fifth semiconductor layer of the second conductivity type in the surface portion of said fourth semiconductor layer;

a first removal step of forming on the surface of said fourth semiconductor layer and a surface of said fifth semiconductor layer a barrier film having an opening surrounding a part of the surface of said fifth semiconductor layer and selectively removing a portion of said fifth semiconductor layer, a portion of said fourth semiconductor layer, and a portion of said third semiconductor layer using said barrier film as a mask to form a trench having a depth extending at least said third semiconductor layer through said fourth semiconductor layer and then removing said barrier film;

a first step of forming an insulating film on surfaces of said trench, said fourth semiconductor layer and said fifth semiconductor layer;

a first deposition step of depositing a conductor on said insulating film to fill said trench;

a second removal step of uniformly removing said conductor to an opening of said trench, leaving said conductor in said trench as a control electrode;

a second deposition step of depositing an insulating layer on the surface of said insulating film and a surface of said conductor buried in said trench;

a third removal step of selectively removing said insulating layer and said insulating film in region covering the surface of said fourth semiconductor layer and a part of the surface of said fifth semiconductor layer;

a step of depositing a conductor on the surface of said fourth and fifth semiconductor layers exposed after said third removal step to form a first main electrode; and

a step of depositing a conductor on said first main surface of said semiconductor substrate to form a second main electrode.

2. The method of maufacturing an insulated gate semiconductor device according to claim 1, wherein said substrate forming step includes steps of,

preparing a semiconductor substrate body of the first conductivity type having two main surfaces, and

depositing a semiconductor layer of the second conductivity type by epitaxial growth on one main surface of said semiconductor substrate body to form said second semiconductor layer.

3. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein said substrate forming step includes steps of,

preparing a semiconductor substrate body of the second conductivity type having two main surfaces,

implanting an impurity of the first conductivity type into one main surface of said semiconductor substrate body, and

diffusing said impurity implanted into said one main surface to form said first semiconductor layer of the first conductivity type.

4. The method of manufacturing an insulated gate semiconductor device according to claim 3, wherein said step of implanting said impurity of the first conductivity type includes steps of,

selectively implanting the impurity of the first conductivity type into said one main surface of said semiconductor substrate body pattern formed.

5. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein said semiconductor substrate formed in said substrate forming step further includes a sixth semiconductor layer of the second conductivity type with a higher impurity concentration than that of said second semiconductor layer interposed between said first semiconductor layer and said second semiconductor layer.

6. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein if impurity concentrations in said second semiconductor layer, said third semiconductor layer and said fourth semiconductor layer are taken as C₂, C₃, and C₄, respectively, said first implantation step and said second implantation step are performed so that C₂<

C₃<

C₄.

7. The method of manufacturing an insulated gate semiconductor device according to claim 1, further comprising a fourth implantation step of implanting and diffusing an impurity of the first conductivity type into at least a part of the surface of said fourth semiconductor layer to form a seventh semiconductor layer having an impurity concentration higher than that of said fourth semiconductor layer in the surface portion of said fourth semiconductor layer.

8. The method of manufacturing an insulated gate semiconductor device according to claim 7, wherein as compared with a dose of the impurity of the second conductivity type in said third implantation step, a dose of the impurity of the first conductivity type in said forth implantation step is so low as not to substantially affect the impurity of the second conductivity type.

9. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein said first removal step includes a step of, after forming said trench, implanting and then diffusing an impurity of the first conductivity type using said barrier film as a mask to form an eighth semiconductor layer of the first conductivity type of an impurity concentration higher than that of said second semiconductor layer in a bottom of said trench.

10. The method of manufacturing an insulated gate semiconductor device according to claim 1, further comprising a step of, after said first removal step, implanting and then diffusing an impurity of the first conductivity type of such a dose as does not substantially affect the impurity concentration of said fifth semiconductor layer into said trench and the exposed surface of said fourth and fifth semiconductor layers to form an eighth semiconductor layer of the first conductivity type with an impurity concentration higher than that of said second semiconductor layer on a bottom of said trench, and at the same time, to form a ninth semiconductor layer with an impurity concentration higher than that of said fourth semiconductor layer in the exposed surface of said fourth semiconductor layer.

12. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein in said third implantation step, said fifth semiconductor layer is so formed as to be divided into plural parts arranged side by side between adjacent ones of which an exposed surface of said fourth semiconductor layer is interposed, and

in said removal step, said trench is so formed as to be divided into a plurality of unit trenches arranged side by side which penetrate said plural parts of said firfth semiconductor layer, respectively.

13. A method of manufacturing an insulated gate semiconductor device, comprising:

a substrate forming step of forming a semiconductor substrate defining first and second main surfaces and having a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, said first semiconductor layer being exposed in said first main surface and said second semiconductor layer being exposed in said second main surface;

a first implantation step of implanting and diffusing an impurity of the second conductivity type into said second main surface of said semiconductor substrate to an impurity concentration higher than the impurity concentration of said second semiconductor layer to form a third semiconductor layer of the second conductivity type in a surface portion of said second semiconductor layer;

a second implantation step of implanting and diffusing an impurity of the first conductivity type into a surface of said third semiconductor layer to form a fourth semiconductor layer of the first conductivity type in a surface portion of said third semiconductor layer;

a third implantation step of selectively implanting and diffusing an impurity of the second conductivity type in a surface of said fourth semiconductor layer to selectively form a fifth semiconductor layer of the second conductivity type in the surface portion of said fourth semiconductor layer;

a first removal step of forming on the surface of said fourth semiconductor layer and a surface of said fifth semiconductor layer a barrier film having an opening surrounding a part of the surface of said fifth semiconductor layer and selectively removing a portion of said fifth semiconductor layer, a portion of said fourth semiconductor layer and a portion of said third semiconductor layer using said barrier film as a mask to form a trench having a depth extending at least said third semiconductor layer through said fourth semiconductor layer and then removing said barrier film;

a first step of forming an insulating film on surfaces of said trench, said fourth semiconductor layer and said fifth semiconductor layer;

a first deposition step of depositing a conductor on said insulating film to fill said trench;

a second removal step of uniformly removing said conductor to an opening of said trench, leaving said conductor in said trench as a control electrode;

a second deposition step of depositing an insulating layer on the surface of said insulating film and a surface of said conductor buried in said trench;

a third removal of selectively removing said insulating layer and a part of the film in the region covering the surface of said fourth semiconductor layer and a part of the surface of said fifth semiconductor layer;

a step of depositing a conductor on the surface of said fourth and fifth semiconductor layers exposed after said third removal step to form a first main electrode; and

a step of depositing a conductor on said first main surface of said semiconductor substrate to form a second main electrode, wherein

said first removal step includes a step of, after forming said trench, implanting and then diffusing an impurity of the first conductivity type using said barrier film as mask to form an eigth semiconductor layer of the first conductivity type of an impurity concentration higher than that of said second semiconductor layer in a bottom of said trench.

14. A method of manufacturing an insulated gate semiconductor device, composing:

a substrate forming step of forming a semiconductor substrate defining first and second main surfaces and having a first semiconductor substrate defining first and second semiconductor layer of a second conductivity type, said first semiconductor layer being exposed in said second main surface;

a first implantation step of implanting and diffusing an impurity of the second conductivity type into said second main surface of said semiconductor substrate to an impurity concentration higher than the impurity concentration of said second semiconductor layer to form a third semiconductor layer of the second conductivity type in a surface portion of said second semiconductor layer;

a second implantation step of implanting and diffusing an impurity of the first conductivity type into a surface of said third semiconductor layer to form a fourth semiconductor layer of the first conductivity type in a surface portion of said third semiconductor layer;

a third implantation step of selectively implanting and diffusing an impurity of the second conductivity type in a surface of said fourth semiconductor layer to selectively form a fifth semiconductor layer of the second conductivity type in the surface portion of said fourth semiconductor layer;

a first removal step of forming on the surface of said fourth semiconductor layer and a surface of said fifth semiconductor layer a barrier film having an opening surrounding a part of the surface of said fifth semiconductor layer and selectively removing a portion of said fifth semiconductor layer, a portion of said fourth semiconductor layer and a portion of said third semiconductor layer using said barrier film as a mask to form a trench having a depth extending at least said third semiconductor layer through said fourth semiconductor layer and then removing said barrier film.

a first step of forming an insulating film on surfaces of said trench, said fourth semiconductor layer and said fifth semiconductor layer;

a first deposition stepof depositing a conductor on said insulating film to fill said trench;

a second removal step of uniformly removing said conductor to an opening of said trench, leaving said conductor in said trench as a control electrode;

a second deposition step of depositing an insulating layer on the surface of said insulating film and a surface of said conductor buried in said trench;

a third removal step of selectively removing said insulating layer and said insulating film in the region covering the surface of said fourth semiconductor layer and a part of the surface of said fifth semiconductor layer;

a step of depositing a conductor on the surface of said fourth and fifth semiconductor layers exposed after said third removal step to form a first main electrode; and

a step of depositing a conductor on said first main surface of said semiconductor substrate to form a second main electrode, wherein

at said third implantation step, said fifth semiconductor layer is so formed as to have plural separated portions arranged side by side and a linking portion selectively linking adjacent ones of said plural separated portions,

at said first removal step, said trench is so formed as to be divided into a plurality of unit trenches arranged side by side and respectively passing through said plural separated portions of said fifth semiconductor layer, and

at said third removal step, said insulating layer and said insulating film are removed in a region covering said fifth semiconductor layer only in said linking portion and said fourth semiconductor layer so that said first main electrode is connected to said fifth semiconductor layer only in said linking portion after said step of depositing said conductor on the surface of said fourth and fifth semiconductor layers.

15. A method of manufacturing an insulated gate semiconductor device, comprising the steps of:

(a) forming a semiconductor substrate defining first and second main surfaces and having a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, said first semiconductor layer being exposed in said first main surface and said second semiconductor layer being exposed in said second main surface;

(b) implanting and diffusing an impurity of said second conductivity type to an impurity concentration higher than an impurity concentration of said second semiconductor layer into said second main surface of said semiconductor substrate to form a third semiconductor layer of said second conductivity type in a surface portion of said second

(c) implanting and diffusing an impurity of said first conductivity type in a surface of said third semiconductor layer to form a fourth semiconductor layer of said first conductivity type in a surface portion of said third semiconductor layer, wherein said third semiconductor layer is so formed as to be thinner after forming said fourth semiconductor layer than said second semiconductor layer remaining;

(d) selectively implanting and diffusing an impurity of said second conductivity type in a surface of said fourth semiconductor layer to selectively form a fifth semiconductor layer of said second conductivity type in a surface portion of said fourth semiconductor layer;

(e) forming an insulating film on exposed surfaces of said fourth and fifth semiconductor layers;

(f) providing a conductor on said insulating film;

(g) selectively removing said conductor to form a control electrode facing a portion of said fourth semiconductor layer interposed between said third and fifth semiconductor layers through said insulating film so that said portion fors a channel region;

(h) selectively removing said insulating film in a region that lies across said surfaces of said fourth and fifth semiconductor layers;

(i) providing a conductor lying across said surfaces of said fourth and fifth semiconductor layers exposed after said step (h) to form a first main electrode; and

(j) providing a conductor on said first main surface of said semiconductor substrate to form a second main electrode.

11. The method of manufacturing an insulated gate semiconductor device according to claim 16, further comprising a step of, after implantation of the impurity of the first conductivity type for forming said eighth semiconductor layer, forming an insulating film on an inner wall of said trench and then removing this insulating film.

16. The method of manufacturing the insulated gate semiconductor device according to claim 15, wherein said step (a) comprises the steps of:

(a-1) preparing a semiconductor substrate body of the first conductivity type having two main surfaces, and

(a-2) providing a semiconductor layer of said conductivity type with a low impurity concentration by the epitaxial growth on one of said main surfaces of said semiconductor substrate body to form said second semiconductor layer.

17. The method of manufacturing the insulated gate semiconductor device according to claim 15, wherein said step (a) comprises the steps of;

(a-1) preparing a semiconductor substrate body of said second conductivity type with a low impurity concentration having two main surfaces,

(a-2) implanting an impurity of said first conductivity type type into one of said main surfaces of said semiconductor substrate body; and

(a-3) diffusing said impurity implanted into said one main surface to form said main semiconductor layer of said first conductivity type.

18. The method of manufacturing the insulated gate semiconductor device according to claim 17, wherein said step (a-2) comprises the step of,

(a-2-1) selectively implanting an impurity of said first conductivity type into said one main surface of said semiconductor substrate body.

19. The method of manufacturing the insulated gate semiconductor device according to claim 15, wherein said semiconductor substrate formed in step (a) further comprises a sixth semiconductor layer of said second conductivity type with a high impurity concentration interposed between said first semiconductor layer and said second semiconductor layer.

20. The method of manufacturing the insulated gate semiconductor device according to claim 15, wherein, if the impurity concentrations in said second semiconductor layer, said third semiconductor layer and said fourth semiconductor layer are taken C2, C3, C4, respectively, said steps (b) and (c) are carried out so that the relation thereof is C2<

C3<

C4.

21. The method of manufacturing an insulated gate semiconductor device according to claim 15, further comprising a step of:

(k) implanting and diffusing an impurity of the first conductivity type into at least a part of the surface of said fourth semiconductor layer to form a seventh semiconductor layer having an impurity concentration higher than that of said fourth semiconductor layer in the surface portion of said fourth semiconductor layer.

22. The method of manufacturing an insulated gate semiconductor device according to claim 21, wherein

said step (d) comprises steps of:

forming a resist pattern selectively having an opening in a surface of said fourth semiconductor layer on the surface of said fourth semiconductor layer; and

implanting and diffusing an impurity of the second conductivity type using the resist pattern as a mask to selectively to selectively form said fifth semiconductor layer of the second conductivity type in a surface portion of said fourth semiconductor layer, and wherein

in said step (k), a resist pattern having a selectively opened opening is formed on the surface of said fourth semiconductor layer, and then using this resist pattern as a mask, the impurity of the first conductivity type is implanted and diffused to selectively form said seventh semiconductor layer in the surface portion of said fourth semiconductor layer, and

the opening of said resist pattern used in said third implantation step and the opening of said resist pattern used in said fourth implantation step selectively open so that said fifth and seventh semiconductor layers occupy different regions in the surface portion of said fourth semiconductor layer.

23. A method of manufacturing an insulated gate semiconductor device, comprising the steps:

(a) forming a semiconductor substrate defining first and second main surfaces and having a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, said first semiconductor layer being exposed in said first surface;

(b) implanting and diffusing an impurity of said first conductivity type in a surface of impurity concentration higher than an impurity concentration of said second semiconductor layer into said second main surface of said semiconductor substrate to form a third semiconductor layer of said second conductivity type in a surface portion of said second semiconductor layer,

(c) implanting and diffusing an impurity of said first conductivity type in a surface of said third semiconductor layer to form a fourth semiconductor layer of said first conductivity type in a surface portion of said third semiconductor layer;

(d) selectively implanting and diffusing an impurity of said second conductivity type in a surface of said fourth semiconductor layer to selectively form a fifth semiconductor layer;

of said second conductivity type in a surface portion of said fourth semiconductor layer;

(e) forming an insulated film on exposed surfaces of said fourth and fifth semiconductor layers;

(f) providing a conductor on said insulating film;

(g) selectively removing said conductor to form a control electrode facing a potion of said fourth semiconductor layer interposed between said third and fifth semiconductor layers through said insulating film so that said portion forms a channel region;

(h) selectively removing said insulating film in a region that lies across said surfaces of said fourth and fifth semiconductor layers;

(i) providing a conductor lying across said surfaces of said fourth and fifth semiconductor layers exposed after said step (h) to form a first main electrode; and

(j) providing a conductor on said first main surface of said semiconductor substrate to form a second main electrode, wherein

at said step (d), said fifth semiconductor layer is so formed as to have a pair of separated portions arranged side by side and a linking portion selectively linking said pair of separated portions,

at said step (g), said conductor is so removed that said control electrode is divided into a pair of unit control electrodes respectively facing portions of said fourth semiconductor layer interposed between said pair of separated portions of said fifth semiconductor layer and said third semiconductor layer, and

at said step (h), said insulating film is removed in a region covering said fifth semiconductor layer only in said linking portion and said fourth semiconductor layer so that said first main electrode is connected to said fifth semiconductor layer only in said linking portion after said step (i).