Method of setting threshold voltage levels of a multiple-valued mask programmable read only memory

• US 6,221,723 B1
• Filed: 09/09/1998
• Issued: 04/24/2001
• Est. Priority Date: 09/10/1997
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kunitou, Masao
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US09/149,110
• Time in Patent Office: 958 Days
• Field of Search: 438/276, 438/277, 438/278, 438/279, 438/275, 438/289, 438/290, 438/291, 438/587
• US Class Current: 438/276
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H10B 20/383 Channel doping programmed

Abstract

A method of setting a plurality of different threshold voltage levels to a plurality of cell regions for a mask programmable semiconductor device by carrying out a second impurity first-code selective ion-implantation, into at least a first-selected one of said plurality of cell regions doped with a first impurity to have a first threshold voltage level so that the at least the first-selected one of said cell regions has a second threshold voltage level which is different from the first threshold voltage level, the second impurity of the first-code selective ion-implantation being heavier than said first impurity so as to suppress any excess thermal diffusion to avoid variations in threshold voltage level of the cell regions.

Claims

1. A method of setting a plurality of different threshold voltage levels to a plurality of cell regions for a mask programmable semiconductor device, said method comprising the steps of:

forming gate electrodes surrounded by a first photo-resist mask;

applying a first ion-implantation dose to simultaneously form drain, source, and channel regions associated with all of the gate electrodes surrounded by the first photo-resist mask;

while retaining the first photo-resist mask, with a first impurity carrying out a second ion-implantation through all of the gate electrodes to establish a first threshold voltage level associated with each of the gate electrodes of all of the cell regions surrounded by the first photo-resist mask, the first ion-implantation being performed at an energy level lower than the second ion-implantation;

discarding the first photo-resist mask and providing a second photo-resist mask protecting the drain and source region and plural ones of the gate electrodes, at least one of the gate electrodes being exposed by the second photo-resist mask; and

with a second impurity applying a first-code selective ion-implantation through at least a first-selected one of the exposed gate electrodes to establish a second threshold voltage level associated with the exposed at least one gate electrode, the second threshold voltage level being different from the first threshold voltage level,

wherein said second impurity of said first-code selective ion-implantation is heavier than said first impurity so as to suppress any excess thermal diffusion to avoid variations in threshold voltage level of said cell regions.

2. The method as claimed in claim 1, wherein said second impurity has an opposite conductivity type to said first impurity.

3. The method as claimed in claim 2, wherein said first impurity comprises boron and said second impurity comprises an n-type impurity heavier than boron.

4. The method as claimed in claim 3, wherein said n-type impurity of said second impurity comprises one selected from the group consisting of P, As and Sb.

5. The method as claimed in claim 2, wherein said first impurity comprises an n-type impurity and said second impurity comprises a p-type impurity heavier than said n-type impurity.

6. The method as claimed in claim 1, wherein said second impurity has the same conductivity type as said first impurity.

7. The method as claimed in claim 6, wherein said first and second impurities are of p-type, and said first impurity comprises boron and said second impurity comprises one selected from the group consisting of boron difluoride, gallium and indium.

8. The method as claimed in claim 7, wherein said first and second impurities are of n-type, and said first impurity comprises phosphorus and said second impurity comprises one selected from the group consisting of arsenic and antimony.

9. The method as claimed in claim 1, further comprising a step of:

carrying out a second-code selective ion-implantation of a third impurity into at least a second-selected one of said plurality of gate electrodes, so that said at least second-selected one of said gate electrodes has a third threshold voltage level which is different from said first and second threshold voltage levels,

wherein said third impurity of said second-code, selective ion-implantation is heavier than said first impurity.

10. The method as claimed in claim 9, wherein said third impurity has an opposite conductivity type to said first impurity.

11. The method as claimed in claim 10, wherein said first impurity comprises boron and said second impurity comprises an n-type impurity heavier than boron.

12. The method as claimed in claim 11, wherein said n-type impurity of said third impurity comprises one selected from the group consisting of P, As and Sb.

13. The method as claimed in claim 10, wherein said first impurity comprises an n-type impurity and said third impurity comprises a p-type impurity heavier than said n-type impurity.

14. The method as claimed in claim 9, wherein said third impurity has the same conductivity type as said first impurity.

15. The method as claimed in claim 14, wherein said first and third impurities are of p-type, and said first impurity comprises boron and said third impurity comprises one selected from the group consisting of boron difluoride, gallium and indium.

16. The method as claimed in claim 15, wherein said first and third impurities are of n-type, and said first impurity comprises phosphorus and said third impurity comprises one selected from the group consisting of arsenic and antimony.

17. The method as claimed in claim 9, wherein said first-code selective ion-implantation of said second impurity and said second-code selective ion-implantation of said third impurity are carried out at different doses from each other.

18. The method as claimed in claim 17, wherein at least one of the date electrodes is subjected to both said first-code selective ion-implantation and subsequent said second-code selective ion-implantation.

19. The method as claimed in claim 1, wherein said first-code selective ion-implantation is carried out at an ion-implantation energy which is higher than when said first impurity is doped into said all cell regions.

20. The method as claimed in claim 9, wherein said second-code selective ion-implantation is carried out at the same ion-implantation energy as said first-code selective ion-implantation.

21. A method of setting multiple different threshold voltage levels to a plurality of cell transistor channel regions for a multiple-valued mask programmable read only memory, said method comprising the steps of:

forming gate electrodes surrounded by a first photo-resist mask;

applying a first ion-implantation dose to simultaneously form drain, source, and cell transistor channel regions intermediate the drain and source regions and associated with all of the gate electrodes surrounded by the first photo-resist mask;

while retaining the first photo-resist mask, with a first impurity carrying out a second ion-implantation through all of the gate electrodes to establish a first threshold voltage level associated with each of the gate electrodes of all of the cell regions surrounded by the first photo-resist mask, the first ion-implantation being performed at an energy level lower than the second ion-implantation;

carrying out a first-code selective ion-implantation, into at least a first-selected one of said plurality of cell transistor channel regions with a second impurity so that said at least the first-selected one of said cell transistor channel regions has a second threshold voltage level which is different from said first threshold voltage levels; and

carrying out a second-code selective ion-implantation of a third impurity into at least second-selected one of said plurality of cell transistor channel regions, so that said at least second-selected one of said cell transistor channel regions has a third threshold voltage level which is different from said first and second threshold voltage levels,

wherein said second impurity of said first-code selective ion-implantation is heavier than said first impurity, and said third impurity of said second-code selective ion-implantation is also heavier than said first impurity, so as to suppress any excess thermal diffusion to avoid variations in threshold voltage level of said cell transistor channel regions, and

wherein at least any one of said second and third impurities has an opposite conductivity type to said first impurity.

22. The method as claimed in claim 21, wherein both said second and third impurities have an opposite conductivity type to said first impurity.

23. The method as claimed in claim 22, wherein said first impurity comprises boron and each of said second and third impurities comprises an n-type impurity heavier than boron.

24. The method as claimed in claim 23, wherein, said n-type impurity of each of said second and third impurities comprises one selected from the group consisting of P, As and Sb.

25. The method as claimed in claim 22, wherein, said first impurity comprises an n-type impurity and each of said second and third impurities comprises a p-type impurity heavier than said n-type impurity.

26. The method as claimed in claim 25, wherein said first impurity comprises an n-type impurity and both said second and third impurities comprises the same p-type impurity heavier than said n-type impurity.

27. The method as claimed in claim 26, wherein said first and second impurities are of p-type, and said first impurity comprises boron and said second impurity comprises one selected from the group consisting of boron difluoride, gallium and indium.

28. The method as claimed in claim 27, wherein said first and second impurities are of n-type, and said first impurity comprises phosphorus and said second impurity comprises one selected from the group consisting of arsenic and antimony.

29. The method as claimed in claim 21, wherein both said second and third impurities have opposite conductivity types to each other.

30. The method as claimed in claim 29, wherein said first impurity comprises boron, said second impurity comprises an n-type impurity heavier than boron, said third impurity comprises a p-type impurity heavier than boron.

31. The method as claimed in claim 30, wherein said n-type impurity of said second impurity comprises one selected from the group consisting of P, As and Sb, and said p-type impurity of said third impurity comprises one selected from the group consisting of boron difluoride, gallium and indium.

32. The method as claimed in claim 29, wherein said first impurity comprises boron, said second impurity comprises a p-type impurity heavier than boron, said third impurity comprises an n-type impurity heavier than boron.

33. The method as claimed in claim 32, wherein said n-type impurity of said third impurity comprises one selected from the group consisting of P, As and Sb, and said p-type impurity of said second impurity comprises one selected from the group consisting of boron difluoride, gallium and indium.

34. The method as claimed in claim 21, wherein said first-code selective ion-implantation of said second impurity and said second-code selective ion-implantation of said third impurity are carried out at different doses from each other.

35. The method as claimed in claim 34, wherein said at least first-selected one of said cell transistor channel regions comprises first-selected plural cell transistor channel regions and said at least first-selected one of said cell transistor channel regions comprises second-selected plural cell transistor channel regions, and wherein said first-selected plural cell transistor channel regions partially overlap said second-selected plural cell transistor channel regions, so that at least an overlapped cell transistor channel region belonging both said first-selected and second-selected plural cell transistor channel regions is subjected to both said first-code selective ion-implantation and subsequent said second-code selective ion-implantation.

36. The method as claimed in claim 21, wherein each of said first-code selective ion-implantation and said second-code selective ion-implantation is carried out at an ion-implantation energy which is higher than when said first impurity is doped into said all cell transistor channel regions.

37. A method of setting multiple different threshold voltage levels to a plurality of cell transistor channel regions formed in a p-type silicon region for a multiple-valued mask programmable read only memory, said method comprising the steps of:

forming gate electrodes surrounded by a first photo-resist mask;

applying a first ion-implantation dose to simultaneously form drain, source, and cell transistor channel regions intermediate the drain and source regions and associated with all of the gate electrodes surrounded by the first photo-resist mask;

while retaining the first photo-resist mask, with a first impurity of boron carrying out a second ion-implantation through all of the gate electrodes to establish a first threshold voltage level associated with each of the gate electrodes of all of the cell regions surrounded by the first photo-resist mask, the first ion-implantation being performed at an energy level lower than the second ion-implantation;

carrying out a first-code selective ion-implantation, into at least a first-selected one of said plurality of cell transistor channel regions with a second impurity of an n-type so that said at least the first-selected one of said cell transistor channel regions has a second threshold voltage level which is different from said first threshold voltage levels; and

carrying out a second-code selective ion-implantation of a third impurity of said n-type into at least a second-selected one of said plurality of cell transistor channel regions, so that said at least second-selected one of said cell transistor channel regions has a third threshold voltage level which is different from said first and second threshold voltage levels,

wherein said second impurity of said first-code selective ion-implantation is heavier than said first impurity, and said third impurity of said second-code selective ion-implantation is also heavier than said first impurity, so as to suppress any excess thermal diffusion to avoid variations in threshold voltage level of said cell transistor channel regions.

38. The method as claimed in claim 37, wherein said n-type impurity of each of said second and third impurities comprises one selected from the group consisting of P, As and Sb.

39. The method as claimed in claim 37, wherein said first-code selective ion-implantation of said second impurity and said second-code selective ion-implantation of said third impurity are carried out at different doses from each other.

40. The method as claimed in claim 39, wherein said at least first-selected one of said cell transistor channel regions comprises first-selected plural cell transistor channel regions and said at least first-selected one of said cell transistor channel regions comprises second-selected plural cell transistor channel regions, and wherein said fire-selected plural cell transistor channel regions partially overlap said second-selected plural cell transistor channel regions, so that at least in overlapped cell transistor channel region belonging both said first-selected and second-selected plural cell transistor channel regions is subjected to both said first-code selective ion-implantation and subsequent said second-code selective ion-implantation.

41. The method as claimed in claim 37, wherein each of said first-code selective ion-implantation and said second-code selective ion-implantation is carried out at an ion-implantation energy which is higher than when boron as said first impurity is doped into said all cell transistor channel regions.

42. A method of setting multiple different threshold voltage levels to a plurality of cell transistor channel regions formed in a p-type silicon region for a multiple-valued mask programmable read only memory, said method comprising the steps of:

forming gate electrodes surrounded by a first photo-resist mask;

applying a first ion-implantation dose to simultaneously form drain, source, and cell transistor channel regions intermediate the drain and source regions and associated with all of the gate electrodes surrounded by the first photo-resist mask;

while retaining the first photo-resist mask, with a first impurity of boron carrying out a second ion-implantation through all of the gate electrodes to establish a first threshold voltage level associated with each of the gate electrodes of all of the cell regions surrounded by the first photo-resist mask, the first ion-implantation being performed at an energy level lower than the second ion-implantation;

carrying out a first-code selective ion-implantation, into at least a first-selected one of said plurality of cell transistor channel regions with a second impurity of a n n-type so that said at least the first-selected one of said cell transistor channel regions has a second threshold voltage level which is different from said first threshold voltage level; and

carrying out a second-code selective ion-implantation of a third impurity of a p-type into at least a second-selected one of said plurality of cell transistor channel regions, so that said at least second-selected one of said cell transistor channel regions has a third threshold voltage level which is different from said first and second threshold voltage levels,

wherein said second impurity of said first-code selective ion-implantation is heavier than said first impurity, and said third impurity of said second-code selective ion-implantation is also heavier than said first impurity, so as to suppress any excess thermal diffusion to avoid variations in threshold voltage level of said cell transistor channel regions.

43. The method as claimed in claim 42, wherein said n-type impurity of said second impurity comprises one selected from the group consisting of P, As and Sb, and said p-type impurity of laid third impurity comprises one selected from the group consisting of boron difluoride, gallium and indium.

44. The method as claimed in claim 42, wherein said first-code selective ion-implantation of said second impurity and said second-code selective ion-implantation of said third impurity are carried out at different doses from each other.

45. The method as claimed in claim 44, wherein said at least first-selected one of said cell transistor channel regions comprises first-selected plural cell transistor channel regions and said at least first-selected one of said cell transistor channel regions comprises second-selected plural cell transistor channel regions, and wherein said first-selected plural cell transistor channel regions partially overlap said second-selected plural cell transistor channel regions, so that at least an overlapped cell transistor channel region belonging both said first-selected and second-selected plural cell transistor channel regions is subjected to both said first-code selective ion-implantation and subsequent said second-code selective ion-implantation.

46. The method as claimed in claim 42, wherein each of said first-code selective ion-implantation and said second-code selective ion-implantation is carried out at an ion-implantation energy which is higher than when boron as said first impurity is doped into said all cell transistor channel regions.

47. A method of setting multiple different threshold voltage levels to a plurality of cell transistor channel regions formed in a p-type silicon region for a multiple-valued mask programmable read only memory, said method comprising the steps of:

forming gate electrodes surrounded by a first photo-resist mask;

applying a first ion-implantation dose to simultaneously form drain, source, and cell transistor channel regions intermediate the drain and source regions and associated with all of the gate electrodes surrounded by the first photo-resist mask;

while retaining the first photo-resist mask, with a first impurity of boron carrying out a second ion-implantation through all of the gate electrodes to establish a first threshold voltage level associated with each of the gate electrodes of all of the cell regions surrounded by the first photo-resist mask, the first ion-implantation being performed at an energy level lower than the second ion-implantation;

carrying out a first-code selective ion-implantation, into at least a first-selected one of said plurality of cell transistor channel regions with a second impurity of an p-type so that said at least the first-selected one of said cell transistor channel regions has a second threshold voltage level which is different from said first threshold voltage levels; and

carrying out a second-code selective ion-implantation of a third impurity of said n-type into at least a second-selected one of said plurality of cell transistor channel regions, so that said at least second-selected one of said cell transistor channel regions has a third threshold voltage level which is different from said first and second threshold voltage levels,

wherein said second impurity of said first-code selective ion-implantation is heavier than said first impurity, and said third impurity of said second-code selective ion-implantation is also heavier than said first impurity, so as to suppress any excess thermal diffusion to avoid variations in threshold voltage level of said cell transistor channel regions.

48. The method as claimed in claim 47, wherein said p-type impurity of said second impurity comprises one selected from the group consisting of boron difluoride, gallium and indium, and said n-type impurity of said third impurity comprises one selected from the group consisting of P, As and Sb.

49. The method as claimed in claim 47, wherein said first-code selective ion-implantation of said second impurity and said second-code selective ion-implantation of said third impurity are carried out at different doses from each other.

50. The method as claimed in claim 49, wherein said at least first-selected one of said cell transistor channel regions comprises first-selected plural cell transistor channel regions and said at least first-selected one of said cell transistor channel regions comprises second-selected plural cell transistor channel regions, and wherein said first-selected plural cell transistor channel regions partially overlap said second-selected plural cell transistor channel regions, so that at least an overlapped cell transistor channel region belonging both said first-selected and second-selected plural cell transistor channel regions is subjected to both said first-code selective ion-implantation and subsequent said second-code selective ion-implantation.

51. The method as claimed in claim 47, wherein each of said first-code selective ion-implantation and said second-code selective ion-implantation is carried out at an ion-implantation energy which is higher than when boron as said first impurity is doped into said all cell transistor channel regions.