Method for bonding single crystal membranes to a curved surface

• US 6,221,739 B1
• Filed: 11/17/1998
• Issued: 04/24/2001
• Est. Priority Date: 08/20/1998
• Status: Expired due to Fees

• Current Assignee: Vladimir A. Gorelik
• Original Assignee: Vladimir A. Gorelik
• Inventors: Gorelik, Vladimir A.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Pham, Thanh V
• Application Number:
  US09/195,169
• Time in Patent Office: 889 Days
• Field of Search: 438/25, 438/26, 438/29, 438/33, 438/39, 438/55, 438/64, 438/68, 438/107, 438/118, 438/119, 438/457, 438/455, 438/456, 438/FOR.369, 438/FOR.409, 438/458, 438/938, 438/962, 148/DIG.12
• US Class Current: 438/455
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/26 Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0132 Binary Alloys
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization
• CPC Class Codes: Y10S 438/962 Quantum dots and lines

Abstract

In accordance with the present invention, a preferred method for bonding a single crystal membrane to a supporting structure having a curved surface includes the steps of segmenting a unitary wafer of a single crystal, for example semiconductor material, into a plurality of semi-attached wafer segments and then aligning a supporting structure with each of the wafer segments. The wafer segments are then detached from each other and are individually bonded to one of the supporting structures. In the case of silicon, lattice strain each of the segments is relieved by depositing a layer of germanium onto the surface of the silicon membrane and then thermally processing the assembly so that germanium atoms are either nucleate on the surface to form quantum wires or diffused into the lattice to relieve the lattice strain.

Claims

1. A method of fabricating a semiconductor element assembly comprising the steps of:

segmenting a unitary wafer of semiconductor material into a plurality of semi-attached wafer segments, each of said serni-attached wafer segments being attached by a wafer bridge to an adjacent one of said wafer segments;

aligning a supporting structure with each of said wafer segments;

detaching each of said wafer segments from each other by severing each of said wafer bridges, and;

bonding each of said wafer segments to one of said supporting structures.

2. The method of claim 1, wherein the step of bonding includes applying heat to each of said supporting structures for adhering said wafer segments to said supporting structures.

3. The method of claim 1, wherein each of said supporting structures includes a non-planar exterior surface, and wherein the step of bonding includes rotating each of said supporting structures relative to each of said wafer segments such that each of said segments align with and engage one of said supporting structures.

4. The method of claim 3, wherein each of said wafer segments is rotated about a rotational axis while each of said supporting structures is rotated about its longitudinal axis such that each of said segments align with and engage one of said supporting structures.

5. The method of claim 1, wherein said semiconductor wafer is a silicon membrane having a characteristic lattice constant and each of said supporting structures includes a non-planar exterior surface, and further including the step of relieving stress of said lattice such that each of said segments deforms to engage with one of said supporting structures.

6. The method of claim 5, further including depositing a layer of polysilicon onto said silicon membrane prior to the step of detaching.

7. The method of claim 5, wherein the step of relieving stress comprises depositing Germanium atoms onto said silicon membrane prior to the step of detaching.

8. The method of claim 7, wherein said silicon membrane is maintained at a temperature no greater than approximately 440 degrees centigrade.

9. The method of claim 8, wherein the temperature of said silicon membrane is elevated above approximately 440 degrees centigrade during the step of bonding such that Germanium atoms are diffused into said lattice.

10. The method of claim 1, wherein the step of bonding occurs in an oxygen containing atmosphere.

11. The method of claim 10, wherein the step of bonding includes depositing a first layer of polysilicon onto each of said wafer segments.

12. The method of claim 11, further including the step of heating each of said supporting structures after the step of depositing said first layer of polysilicon.

13. The method of claim 12, further including the step of oxidizing said first layer of polysilicon.

14. The method of claim 13, further including the step of removing the first layer of polysilicon after said first layer has oxidized.

15. The method of claim 1, wherein each of said supporting structures has a first layer of polysilicon formed thereon prior to the step of bonding.

16. The method of claim 15, wherein said segmented wafer segments are bonded to said supporting structures in an oxidant free atmosphere.

17. The method of claim 16, wherein the step of bonding includes depositing a second layer of polysilicon onto each of said wafer segments such that each of said, wafer segments is disposed between said first and second layers of polysilicon.

18. The method of claim 17, further including the step of heating each of said supporting structures after the step of depositing said first layer of polysilicon.

19. The method of fabrication of claim 18, wherein the step of heating is continued until said first layer of polysilicon melts.

20. The method of claim 19, further including the step of allowing said first polysilicon layer to recrystalize, and then removing said second layer of polysilicon.