Semiconductor device and production thereof

• US 6,221,749 B1
• Filed: 08/31/1999
• Issued: 04/24/2001
• Est. Priority Date: 09/02/1998
• Status: Expired due to Fees

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Horiuchi, Michio, Takeuchi, Yukiharu, Kirloskar, Mohan
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/388,080
• Time in Patent Office: 602 Days
• Field of Search: 298/40, 298/45, 438/117, 438/111, 438/667, 438/455, 438/464, 438/611, 438/461, 438/411
• US Class Current: 438/611
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02319 by using a preform
• CPC Class Codes: H01L 2224/02335 Free-standing redistribution layers
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device comprising a semiconductor chip having an electrode terminal carrying surface and electrode terminals formed on, and carried by, the electrode terminal carrying surface; leads extending substantially parallel to the electrode terminal carrying surface and each having at least one curved portion; a first bump and a second bump which are formed on one and the other ends, respectively, of each of the leads and protrude from the ends in opposite directions toward and away from, respectively, the electrode terminal carrying surface; and the electrode terminals of the semiconductor chip each being bonded to a top of the first bump of the lead to support the leads at a distance from the electrode terminal carrying surface of the semiconductor chip. A process of producing the semiconductor device a dissolvable metal sheet suitably used in the process and a process of producing the metal sheet are also provided.

Claims

1. A process of producing a dissolvable metal sheet suitably applicable to production of semiconductor devices, comprising the steps of:

forming, on one side of a dissolvable metal substrate, a plurality of concavities in positions corresponding to those of electrode terminals of a semiconductor chip or a semiconductor wafer;

filling the concavities with first plated deposits of a first metal;

forming leads on said one side of the substrate, said leads lying on said one side of the substrate and each having at least one curved portion and bonded on one end to at least one of the first plated deposits; and

forming, on the other end of the leads, a plurality of second plated deposits of a second metal having a height greater than that of the leads.

2. The process of claim 1 wherein the dissolvable metal comprises copper, and wherein the first and second metals comprise one or more of gold, nickel, palladium, and solder.

3. The process of claim 1 wherein the dissolvable metal substrate has a thickness of about 0.5 mm and wherein the concavities have a depth of about 0.2 mm.

4. The process of claim 1 wherein the forming leads on said one side of the substrate includes applying a photosensitive resist layer on the substrate;

exposing the resist layer to form a resist pattern that defines the boundary of each lead such that within the boundary is at least a portion of a first plated deposit; and

plating one or more metals within the pattern to form the lead.

5. The process of claim 4 wherein the plating of one or more metals is by electroplating with the substrate used as a plating current supplier and with the resist pattern a s a plating mask.

6. A process of producing a dissolvable metal sheet suitably applicable to production of semiconductor devices, comprising the steps of:

forming throughholes extending through a dissolvable metal substrate in positions corresponding to those of electrode terminals of a semiconductor chip or a semiconductor wafer;

filling the throughholes with a low melting point metal;

forming leads on one side of the substrate, said leads lying on said one side of the substrate and each having at least one curved portion and bonded on one end to the low melting point metal filled in the throughholes; and

forming, on the other end of the leads, a plated deposit of a metal having a height greater than that of the leads.

7. The process of claim 6 wherein the dissolvable metal comprises copper, and wherein the low melting point metal comprises one or more of gold, tin, or solder.

8. The process of claim 6 wherein the forming leads on said one side of the substrate includes applying a photosensitive resist layer on the substrate;

exposing the resist layer to form a resist pattern that defines the boundary of each lead such that within the boundary is at least a portion of the first plated deposit; and

plating one or more metals within the pattern to form the lead so that the lead contacts the low melting point metal.

9. A process for producing a semiconductor device, comprising the steps of:

preparing a dissolvable metal sheet including a dissolvable metal substrate having concavities on one side in positions corresponding to those of electrode terminals formed on an electrode terminal carrying surface of a semiconductor chip or a semiconductor wafer; and

leads lying on said one side of the substrate and each having at least one curved portion, a first connection terminal on one end and a second connection terminal on the other end, the first and second connection terminals protruding in opposite directions from said one side of the substrate, the first connection terminals filling the concavities of the substrate, the second connection terminals having a height greater than that of the leads;

the dissolvable metal substrate being dissolvable by an etchant which does not dissolve the leads and the first and second terminals;

placing the metal substrate with said one side being substantially parallel to said electrode terminal carrying surface of the semiconductor chip or the semiconductor wafer and with the second connection terminals being in an aligned contact with said electrode terminals;

bonding the second connection terminals to the electrode terminals;

entirely removing the metal substrate by dissolution with an etchant to expose lead assemblies each composed of the lead having on said one end the first connection terminal forming an external connection terminal and, on said other end, the second connection terminal forming an electrode connection terminal bonded to the electrode terminal to support the lead at a distance from and substantially parallel to said electrode terminal carrying surface of the semiconductor chip or the semiconductor wafer.

10. The process of claim 9 wherein the dissolvable metal substrate comprises copper with a thickness of about 0.5 mm and wherein the concavities have a depth of about 0.2 mm.

11. The process of claim 9 wherein the leads on said one side of the substrate are formed by applying a photosensitive resist layer on the substrate;

exposing the resist layer to form a resist pattern that defines the boundary of each lead such that within the boundary is at least a portion of the first plated deposit; and

plating one or more metals within the pattern.

12. The process of claim 9 wherein the leads have a resiliency to mitigate stress occurring between the semiconductor chip or semiconductor wafer and the external connection terminals.

13. A process for producing a semiconductor device, comprising the steps of:

preparing a dissolvable metal sheet including a dissolvable metal substrate having concavities on one side in positions corresponding to those of electrode terminals formed on an electrode terminal carrying surface of a semiconductor chip or a semiconductor wafer; and

leads lying on said one side of the substrate and each having at least one curved portion, a first connection terminal on one end and a second connection terminal on the other end, the first and second connection terminals protruding in opposite directions from said one side of the substrate, the first connection terminals filling the concavities of the substrate, the second connection terminals having a height greater than that of the leads;

the dissolvable metal substrate being dissolvable by an etchant which does not dissolve the leads and the first and second terminals;

partially removing the metal substrate by dissolution with an etchant from the other side of the substrate until the first connection terminals are partially exposed;

placing the metal substrate with said one side being substantially parallel to said electrode terminal carrying surface of the semiconductor chip or the semiconductor wafer and with the partially exposed first connection terminals being in an aligned contact with said electrode terminals;

bonding the first connection terminals to the electrode terminals; and

entirely removing the metal substrate by further dissolution with an etchant to expose lead assemblies each composed of the lead having on said one end the first connection terminal forming an electrode connection terminal bonded to the electrode terminal to support the lead at a distance from and substantially parallel to said electrode terminal carrying surface of the semiconductor chip or the semiconductor wafer and, on said other end, the second connection terminal forming an external connection terminal.

14. The process of claim 13 wherein the dissolvable metal sheet has a thickness of about 0.5 mm and wherein the concavities have a depth of about 0.2 mm.

15. The process of claim 13 wherein the second connection terminal comprises one or more of gold, nickel, palladium, and solder.

16. The process of claim 13 wherein the first connection terminal comprises gold.

17. A process for producing a semiconductor device, comprising the steps of:

preparing a dissolvable metal sheet including a dissolvable metal substrate having throughholes extending therethrough in positions corresponding to those of electrode terminals of a semiconductor chip or a semiconductor wafer;

leads formed on one side of the substrate and each having at least one curved portion, a first connection terminal on one end and a second connection terminal on the other end, the first and second connection terminals protruding in opposite directions from said one side of the substrate, the first connection terminals filling the throughholes of the substrate, the second connection terminals having a height greater than that of the leads; and

the dissolvable metal substrate being dissolvable by an etchant which does not dissolve the leads and the first and second terminals;

placing the metal substrate with said one side thereof being substantially parallel to said electrode terminal carrying surface of said semiconductor chip or the semiconductor wafer and with the second connection terminals being in an aligned contact with said electrode terminals;

bonding the second connection terminals to the electrode terminals;

entirely removing the metal substrate by dissolution with an etchant to expose lead assemblies each composed of the lead having on one end the first connection terminal forming an external connection terminal and, on the other end, the second connection terminal forming an electrode connection terminal bonded to the electrode terminal to support the lead at a distance from, and substantially parallel to, said electrode terminal carrying surface of the semiconductor chip or the semiconductor wafer.

18. The process of claim 17 wherein the dissolvable metal sheet comprises copper and has a thickness of about 0.5 mm, and wherein the throughholes have a diameter of about 0.15 mm.

19. A process for producing a semiconductor device, comprising the steps of:

preparing a dissolvable metal sheet including a dissolvable metal substrate having throughholes extending therethrough in positions corresponding to those of electrode terminals of a semiconductor chip or a semiconductor wafer;

leads formed on one side of the substrate and each having at least one curved portion, a first connection terminal on one end and a second connection terminal on the other end, the first and second connection terminals protruding in opposite directions from said one side of the substrate, the first connection terminals filling the throughholes of the substrate and being exposed from the other side of the substrate, the second connection terminals having a height greater than that of the leads; and

the dissolvable metal substrate being dissolvable by an etchant which does not dissolve the leads and the first and second terminals;

placing the metal substrate with said other side being substantially parallel to said electrode terminal carrying surface of said semiconductor chip or the semiconductor wafer and with the first connection terminals exposed from other side being in an aligned contact with said electrode terminals;

bonding the first connection terminals to the electrode terminals;

entirely removing the metal substrate by dissolution with an etchant to expose lead assemblies each composed of the lead having on one end the first connection terminal forming an electrode connection terminal bonded to the electrode terminal to support the lead at a distance from and substantially parallel to said electrode terminal carrying surface of the semiconductor chip or the semiconductor wafer and, on the other end, the second connection terminal forming an external connection terminal.

20. The process of claim 19 wherein the dissolvable metal sheet comprises copper and has a thickness of about 0.5 mm.