Wafer fabrication of die-bottom contacts for electronic devices

• US 6,221,751 B1
• Filed: 06/26/1998
• Issued: 04/24/2001
• Est. Priority Date: 01/24/1997
• Status: Expired due to Fees

• Current Assignee: Chip Systems Innovations, LLC
• Original Assignee: Chipscale
• Inventors: Young, James L., Chen, Changsheng, Marcoux, Phil P., Sander, Wendell B.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US09/105,504
• Time in Patent Office: 1,033 Days
• Field of Search: 438/612, 438/613, 438/614, 438/617, 438/618, 438/624, 438/110, 438/112, 438/113, 438/458, 438/459, 438/460, 438/462, 438/464, 257/784, 257/773, 257/787, 257/780, 257/501, 257/506
• US Class Current: 438/612
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/13008 Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53242 the principal metal being a noble metal, e.g. gold
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A packaging technique for electronic devices includes wafer fabrication of contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. In one embodiment, a trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold wire extends from a connection point within the circuit into the trench. The gold wire may run over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back thinned to expose the bottom surface of the gold wire. Either the back thinning is selective so as to form a substrate standoff, or an epoxy standoff is applied to the bottom of the substrate. A solderable wire runs onto the standoff from the gold wire exposed on the protrusion, possibly over another insulation layer. If an insulative substrate is used, the insulation layers may be optional. Sawing separates the electronic devices and completes their fabrication, without a subsequent assembly step. In another embodiment, the trench in which the gold wires and the solderable wires connect is formed from the bottom of the substrate after it has been epoxy encapsulated. Optionally, the bottom surface of the substrate of the finished device drops down to be co-planar with the contact bottom surfaces, so as to conduct heat out of the device.

Claims

1. A method of fabricating a contact for an electronic device, comprising:

forming a trench in the top surface of a substrate, the substrate having an electronic circuit that includes a connection point;

forming an upper wire above the substrate, the upper wire running from the connection point into the trench;

forming an encapsulant layer above the upper wire and the substrate, the encapsulant layer forming a protrusion in the trench;

thinning the bottom surface of the substrate under at least a portion of the encapsulant protrusion so as to expose at least a portion of the bottom surface of the upper wire;

forming a standoff below the bottom surface of the substrate; and

forming a lower wire that runs from the exposed portion of the upper wire onto the standoff.

2. The method of claim 1, further comprising:

forming an upper insulation layer located between the substrate and the upper wire, the upper insulation layer having a contact through-hole at the connection point and not covering at least a portion of the trench; and

forming a lower insulation layer located between the substrate and the lower wire, the lower insulation layer not covering at least a portion of the bottom surface of the upper wire on the encapsulant protrusion.

3. The method of claim 1, wherein the trench forming includes cutting a starter trench and thereafter etching the starter trench to form the trench.

4. The method of claim 1, wherein the thinning is patterned so as to leave a portion of the bottom surface of the substrate substantially co-planar with the lower wire.

5. The method of claim 1, wherein the substrate is formed of material selected from the group consisting essentially of silicon, gallium arsenide, silicon germanium, silicon carbide, gallium phosphide, ceramic materials, sapphire and quartz.

6. The method of claim 1, wherein the electronic circuit is selected from the group consisting of an integrated circuit fabricated using the substrate, an electronic circuit fabricated using the substrate, an active discrete electronic component fabricated using the substrate, a passive discrete electronic component fabricated using the substrate, an integrated circuit attached to the substrate, an electronic circuit attached to the substrate, an active discrete electronic component attached to the substrate, and a passive discrete electronic component attached to the substrate.

7. The method of claim 1, wherein the upper wire is formed of material selected from the group consisting essentially of gold, silver, copper, aluminum, nickel, and layers thereof.

8. The method of claim 1, wherein the encapsulant is formed of material selected from the group consisting essentially of epoxy, plastic, glass, polymide resin, Teflon, silicon oxide, silicon nitride, silicon, polysilicon, amorphous silicon, aluminum, diamond, and layers thereof.

9. The method of claim 1, wherein the lower wire is formed of material selected from the group consisting essentially of gold, silver, nickel, nichrome-gold, nichrome-nickel, nickel-arsenic-gold, nickel-arsenic, nickel-gold, gold-tin-oxide, palladium-silicide, titanium, tungsten, titanium-tungsten, indium titanium oxide, aluminum, copper, platinum, alloys thereof, and layers thereof.

10. The method of claim 2, wherein the upper insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, patternable plastics, mixtures thereof, and layers thereof.

11. The method of claim 2, wherein the lower insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, patternable plastics, mixtures thereof, and layers thereof.

12. A method of fabricating a contact for an electronic device, comprising:

forming a trench in the top surface of a substrate, the substrate having an electronic circuit that includes a connection point;

forming an upper wire above the substrate, the upper wire running from the connection point into the trench;

forming an encapsulant layer above the upper wire and the substrate, the encapsulant layer forming a protrusion in the trench;

thinning the bottom surface of the substrate under at least a portion of the encapsulant protrusion so as to expose at least a portion of the bottom surface of the upper wire, the thinning being patterned so as to form a substrate standoff; and

forming a lower wire that runs from the exposed portion of the upper wire onto the substrate standoff.

13. The method of claim 12, further comprising:

forming an upper insulation layer located between the substrate and the upper wire, the upper insulation layer having a contact through-hole at the connection point and not covering at least a portion of the trench; and

forming a lower insulation layer located between the substrate and the lower wire, the lower insulation layer not covering at least a portion of the bottom surface of the upper wire on the encapsulant protrusion.

14. The method of claim 12, wherein the trench forming includes cutting a starter trench and thereafter etching the starter trench to form the trench.

15. The method of claim 12, wherein the thinning is patterned so as to leave a portion of the bottom surface of the substrate substantially co-planar with the lower wire.

16. The method of claim 12, wherein the substrate is formed of material selected from the group consisting essentially of silicon, gallium arsenide, silicon germanium, silicon carbide, gallium phosphide, ceramic materials, sapphire and quartz.

17. The method of claim 12, wherein the electronic circuit is selected from the group consisting of an integrated circuit fabricated using the substrate, an electronic circuit fabricated using the substrate, an active discrete electronic component fabricated using the substrate, a passive discrete electronic component fabricated using the substrate, an integrated circuit attached to the substrate, an electronic circuit attached to the substrate, an active discrete electronic component attached to the substrate, and a passive discrete electronic component attached to the substrate.

18. The method of claim 12, wherein the upper wire is formed of material selected from the group consisting essentially of gold, silver, copper, aluminum, nickel, and layers thereof.

19. The method of claim 12, wherein the encapsulant is formed of material selected from the group consisting essentially of epoxy, plastic, glass, polymide resin, Teflon, silicon oxide, silicon nitride, silicon, polysilicon, amorphous silicon, aluminum, diamond, and layers thereof.

20. The method of claim 12, wherein the lower wire is formed of material selected from the group consisting essentially of gold, silver, nickel, nichrome-gold, nichrome-nickel, nickel-arsenic-gold, nickel-arsenic, nickel-gold, gold-tin-oxide, palladium-silicide, titanium, tungsten, titanium-tungsten, indium titanium oxide, aluminum, copper, platinum, alloys thereof, and layers thereof.

21. The method of claim 13, wherein the upper insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, patternable plastics, mixtures thereof, and layers thereof.

22. The method of claim 13, wherein the lower insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, patternable plastics, mixtures thereof, and layers thereof.

23. A method of fabricating a contact for an electronic device, comprising:

forming an upper wire above the top surface of a substrate, the substrate having an electronic circuit that includes a connection point, the upper wire having an inner portion connected to the connection point and an outer portion extending beyond the edge of the electronic circuit;

forming an encapsulant layer above the upper wire and the substrate;

thinning the bottom surface of the substrate under the outer portion of the upper wire so as to expose a portion of its bottom surface, the thinning being patterned so as to form a substrate standoff; and

forming a lower wire that runs from the exposed portion of the upper wire onto the substrate standoff.

24. The method of claim 23, further comprising:

forming an upper insulation layer located between the substrate and the upper wire, the upper insulation layer having a contact through-hole at the connection point and not covering at least a portion of the trench; and

forming a lower insulation layer located between the substrate and the lower wire, the lower insulation layer not covering at least a portion of the bottom surface of the upper wire on the encapsulant protrusion.

25. The method of claim 23, wherein the trench forming includes cutting a starter trench and thereafter etching the starter trench to form the trench.

26. The method of claim 23, wherein the thinning is patterned so as to leave a portion of the bottom surface of the substrate substantially co-planar with the lower wire.

27. The method of claim 23, wherein the substrate is formed of material selected from the group consisting essentially of silicon, gallium arsenide, silicon germanium, silicon carbide, gallium phosphide, ceramic materials, sapphire and quartz.

28. The method of claim 24, wherein the electronic circuit is selected from the group consisting of an integrated circuit fabricated using the substrate, an electronic circuit fabricated using the substrate, an active discrete electronic component fabricated using the substrate, a passive discrete electronic component fabricated using the substrate, an integrated circuit attached to the substrate, an electronic circuit attached to the substrate, an active discrete electronic component attached to the substrate, and a passive discrete electronic component attached to the substrate.

29. The method of claim 24, wherein the upper wire is formed of material selected from the group consisting essentially of gold, silver, copper, aluminum, nickel, and layers thereof.

30. The method of claim 24, wherein the encapsulant is formed of material selected from the group consisting essentially of epoxy, plastic, glass, polymide resin, Teflon, silicon oxide, silicon nitride, silicon, polysilicon, amorphous silicon, aluminum, diamond, and layers thereof.

31. The method of claim 24, wherein the lower wire is formed of material selected from the group consisting essentially of gold, silver, nickel, nichrome-gold, nichrome-nickel, nickel-arsenic-gold, nickel-arsenic, nickel-gold, gold-tin-oxide, palladium-silicide, titanium, tungsten, titanium-tungsten, indium titanium oxide, aluminum, copper, platinum, alloys thereof, and layers thereof.

32. The method of claim 25, wherein the upper insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, patternable plastics, mixtures thereof, and layers thereof.

33. The method of claim 25, wherein the lower insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, patternable plastics, mixtures thereof, and layers thereof.

34. A method of fabricating a contact for an electronic device, comprising:

forming an upper wire above the top surface of a substrate, the substrate having an electronic circuit that includes a connection point, the upper wire having an inner portion connected to the connection point and an outer portion extending beyond the edge of the electronic circuit;

forming an encapsulant layer above the upper wire and the substrate;

thinning the bottom surface of the substrate under the outer portion of the upper wire so as to expose a portion of its bottom surface;

forming a standoff below the bottom surface of the substrate; and

forming a lower wire that runs from the exposed portion of the upper wire onto the standoff.

35. The method of claim 34, further comprising:

forming an upper insulation layer located between the substrate and the upper wire, the upper insulation layer having a contact through-hole at the connection point and not covering at least part of the outer portion of the upper wire; and

forming a lower insulation layer located between the substrate and the lower wire, the lower insulation layer not covering at least part of the outer portion of the upper wire.

36. The method of claim 34, wherein the trench substrate thinning includes forming a starter cut and thereafter etching the starter cut.

37. The method of claim 34, wherein the thinning is patterned so as to leave a portion of the bottom surface of the substrate substantially co-planar with the lower wire.

38. The method of claim 34, wherein the substrate is formed of material selected from the group consisting essentially of silicon, gallium arsenide, silicon germanium, silicon carbide, gallium phosphide, ceramic materials, sapphire and quartz.

39. The method of claim 34, wherein the electronic circuit is selected from the group consisting of an integrated circuit fabricated using the substrate, an electronic circuit fabricated using the substrate, an active discrete electronic component fabricated using the substrate, a passive discrete electronic component fabricated using the substrate, an integrated circuit attached to the substrate, an electronic circuit attached to the substrate, an active discrete electronic component attached to the substrate, and a passive discrete electronic component attached to the substrate.

40. The method of claim 34, wherein the upper wire is formed of material selected from the group consisting essentially of gold, silver, copper, aluminum, nickel, and layers thereof.

41. The method of claim 34, wherein the encapsulant is formed of material selected from the group consisting essentially of epoxy, plastic, glass, polymide resin, Teflon, silicon oxide, silicon nitride, silicon, polysilicon, amorphous silicon, aluminum, diamond, and layers thereof.

42. The method of claim 34, wherein the lower wire is formed of material selected from the group consisting essentially of gold, silver, nickel, nichrome-gold, nichrome-nickel, nickel-arsenic-gold, nickel-arsenic, nickel-gold, gold-tin-oxide, palladium-silicide, titanium, tungsten, titanium-tungsten, indium titanium oxide, aluminum, copper, platinum, alloys thereof, and layers thereof.

43. The method of claim 35, wherein the upper insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, patternable plastics, mixtures thereof, and layers thereof.

44. The method of claim 35, wherein the lower insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, patternable plastics, mixtures thereof, and layers thereof.