Method for integrated circuit power and electrical connections via through-wafer interconnects

• US 6,221,769 B1
• Filed: 03/05/1999
• Issued: 04/24/2001
• Est. Priority Date: 03/05/1999
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nowka, Kevin John, Dhong, Sang Hoo, Shapiro, Michael Jay
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Zarneke, David A
• Application Number:
  US09/263,031
• Time in Patent Office: 781 Days
• Field of Search: 438/667
• US Class Current: 438/667
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA

Abstract

A method for providing a through wafer connection to an integrated circuit silicon package. A hole is first created in the silicon package with an inner surface area extending from the bottom surface of the silicon package to the top surface of the silicon package. The hole is created by one of two methods. The first involves mechanical drilling with a diamond bit rotated at a high rate of speed. The second involves ultrasonically milling utilizing a slurry and steel fingers. The inner surface area of the hole is covered with an insulating material to insulate the conductive material which is later deposited and to serve as a diffusion barrier, then a seed material is placed in the hole. Finally, the hole is filled with a conductive material which is utilized to provide large power inputs or signaling connections to the integrated circuit chips.

Claims

1. A method for making a semiconductor material carrier with electrical connections extending directly through said semiconductor material carrier, said method comprising the steps of:

mechanically creating a hole completely through said semiconductor material carrier, said hole defining an inner surface extending from a first planar surface of said carrier to a second planar surface of said carrier;

insulating said inner surface of said hole utilizing an insulating material that also serves as a diffusion barrier;

depositing a seed material in said hole;

plating said semiconductor material carrier to deposit conductive material on to said inner surface of said hole to extend from said first to said second planar surfaces of said semiconductor material carrier; and

removing any excess deposited conductive material from said first and second planar surface.

2. The method of claim 1, further comprising the steps of:

providing a contact at said top surface for receiving a pin connector of an integrated circuit chip; and

coupling said contact to said conductive material at said top surface of said substrate.

3. The method of claim 1, wherein said creating step creates a plurality of said holes and further comprises the steps of:

simultaneously creating a first plurality of holes in said semiconductor material carrier at said preset distance from each other; and

simultaneously creating a second plurality of holes in said semiconductor material carrier at said preset distance from each other, said second plurality of holes being formed in a different location from said first plurality of holes.

4. The method of claim 3, wherein said mechanically creating step produces a hole with an even bore throughout said semiconductor material carrier from said first planar surface to said bottom planar surface by drilling through said semiconductor material carrier utilizing a drill bit.

5. The method of claim 3, wherein said mechanically creating step produces a through hole with an even bore from said first planar surface to said second planar surface by ultrasonically milling said semiconductor material carrier utilizing a slurry.

6. The method of claim 1, wherein said insulating step further comprises the steps of depositing said insulating material via chemical vapor deposition.

7. The method of claim 1, wherein said depositing step further comprises the step of depositing said seed material via physical vapor deposition.

8. The method of claim 1, wherein said plating step further comprises the step of:

electroplating said hole in said semiconductor material carrier with said conductive material; and

polishing off an excess of said conductive material from said [top surface of said package utilizing chemical mechanical polishing, said excess being deposited during said electroplating step.

9. The method of claim 1, wherein said placing step utilizes a seed material which is the same as said conductive material utilized in said filling step.

10. The method of claim 9, wherein said filling step utilizes a copper-based material as said conductive material.

11. The method of claim 1, wherein said semiconductor material carrier comprises a multilevel wiring running along one of said first and second planar surfaces of said semiconductor material carrier and having a connection point for attaching an integrated circuit chip, said method further comprising coupling said conductive material to said multilevel wiring.

12. The method of claim 1, wherein said conductive material of said filling step has a connection point extending below said package, said method further comprising connecting said integrated circuit to other electronic components utilizing said connection point.

13. A method for providing electrical power supply and external connections directly through a semiconductor substrate, said method comprising the steps of:

mechanically creating a hole in said semiconductor substrate, said hole defining an inner surface extending from a bottom surface of said semiconductor substrate to a top surface of said semiconductor substrate;

insulating said inner surface of said hole utilizing an insulating material that also serves as a diffusion barrier;

depositing a seed material in said hole;

plating said semiconductor substrate to deposit conductive material on to said inner surface of said hole to extend from the top surface to the bottom surface of the semiconductor substrate;

removing any excess deposited conductive material from said top and bottom surface;

coupling said conductive material to an integrated circuit chip; and

connecting said conductive material with other electronic components including an electrical power unit.

14. The method of claim 13, further comprising the steps of:

providing a contact on said top surface for connecting said integrated circuit chip; and

coupling said contact to said conductive material at said top surface and to said integrated circuit chip.

15. The method of claim 13, said mechanically creating step further comprising the steps of:

simultaneously creating a first plurality of holes in said semiconductor substrate at a preset distance from each other; and

simultaneously creating a second plurality of holes in said semiconductor substrate at said preset distance from each other, said second plurality of holes being formed in a different location from said first plurality of holes.

16. The method of claim 15, wherein said mechanically creating step includes the step of creating said hole by drilling through said semiconductor substrate utilizing a drill bit to produce a through hole with an even bore from said top surface to said bottom surface, while holding said semiconductor substrate in a stationary position.

17. The method of claim 15, wherein said mechanically creating step includes the step of creating said hole by ultrasonically milling said package utilizing a slurry to produce a through hole with an even bore from said top surface to said bottom surface.

18. The method of claim 13, wherein said insulating step further comprises the step of depositing said insulating material via chemical vapor deposition.

19. The method of claim 13, wherein said insulating step comprises the step of depositing silicon nitrate on a wall of said hole.

20. The method of claim 13, wherein said plating step utilizes a conductive material which is the same as the material utilized in said depositing step.

21. The method of claim 13, wherein said semiconductor substrate consists of a multilevel wiring running along the top surface, wherein said multilevel wiring has a connection to said integrated circuit chip, said method further comprising coupling said conductive material to said multilevel wiring.

22. The method of claim 13, wherein said conductive material of said plating step has a connector extending below said package, said method further comprising the step of connecting said integrated circuit to other electronic components including a power supply utilizing said connector.