Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein

• US 6,221,779 B1
• Filed: 06/17/1998
• Issued: 04/24/2001
• Est. Priority Date: 07/28/1992
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Dennison, Charles H, Doan, Trung T.
• Primary Examiner(s): Tsai, Jey
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/099,047
• Time in Patent Office: 1,042 Days
• Field of Search: 438/700, 438/620, 438/622, 438/634, 438/623, 438/624, 438/637, 438/666, 438/671, 438/740, 438/734, 438/736
• US Class Current: 438/700
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: Y10S 438/95 Multilayer mask including nonradiation sensitive layer
• CPC Class Codes: Y10S 438/97 Specified etch stop material

Abstract

A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.

Claims

1. A method of defining an opening within a semiconductor device insulation layer, comprising:

etching said semiconductor device insulation layer according to a first mask and a second mask, wherein said first and second masks are identically patterned; and

further etching said insulation layer according to said first mask and a third mask, wherein said first and third masks are differently patterned.

2. The method in claim 1, wherein:

said step of etching said semiconductor device insulation layer comprises etching said insulation layer according to said first mask and said second mask overlying said first mask; and

said step of further etching said insulation layer comprises further etching said insulation layer according to said first mask and said third mask overlying said first mask.

3. The method in claim 2, wherein said step of further etching said insulation layer according to said first mask and said third mask overlying said first mask comprises etching said insulation layer according to said first mask and said third mask contacting said first mask.

4. The method in claim 2, wherein said step of further etching said insulation layer according to said first mask and said third mask overlying said first mask comprises etching said insulation layer according to said first mask and said third mask extending lower than said first mask.

5. A method of forming an opening in a semiconductor device, comprising:

etching a first portion of said opening using a first etch mask defining a first length and a first width along said semiconductor device;

etching a second portion of said opening using a second etch mask and a third etch mask, wherein said second etch mask defines said first width; and

allowing said third etch mask to define a width greater than said first width.

6. The method in claim 5, wherein said step of etching a second portion of said opening comprises using a third etch mask defining a length less than said first length.

7. The method in claim 6, wherein said step of etching a second portion of said opening comprises using a second etch mask defining said first length.

8. The method in claim 7, further comprising a step of preventing said third etch mask from defining a width less than said first width.

9. The method in claim 8, wherein said step of etching a first portion of said opening comprises defining a first depth within said semiconductor device.