Semiconductor integrated circuit device

• US 6,222,213 B1
• Filed: 06/21/1999
• Issued: 04/24/2001
• Est. Priority Date: 06/29/1998
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Fujiwara, Makoto
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/336,781
• Time in Patent Office: 673 Days
• Field of Search: 257/210, 257/203, 257/207, 257/499, 257/211, 257/208, 257/784, 257/786, 257/212
• US Class Current: 257/210
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In order that an internal logic circuit area and an outside input/output cell group are easily connected, a plurality of input/output cell groups for performing signal transfer with an external device are each arranged in a square loop so that the internal logic circuit area is surrounded by a plurality of loops. In each of the inside and the outside input/output cell groups, bonding pads are provided, and square-loop-shaped power supply wiring having an input/output element and protecting element formed area formed therein and functioning as a guard band is disposed on the internal logic circuit area side of the bonding pad. The input/output cells of the inside input/output cell group are arranged in a condition where a first space for providing wiring between the internal logic circuit area and the outside input/output cell group is provided. The inside input/output cell group and the outside input/output cell group are disposed in a condition where the first space for providing wiring between the internal logic circuit area and the outside input/output cell group is provided.

Claims

1. A semiconductor integrated circuit device in which a plurality of input/output cell groups each comprising a plurality of input/output cells for performing signal transfer with an external device are each arranged in a loop so that an internal logic circuit area is surrounded by a plurality of loops,

wherein a bonding pad for performing signal transfer with the external device is provided in each of the input/output cells of inside and outside input/output cell groups of the plurality of input/output cell groups, wherein first guard bands are disposed on an internal logic circuit area side of the bonding pad in each of the input/output cells of the inside input/output cell group, wherein said input/output cells of the inside input/output cell group are arranged in a condition where a first space for providing wiring between the internal logic circuit area and the input/output cells of the outside input/output cell group is provided, and wherein said inside input/output cell group and said outside input/output cell group are arranged in a condition where a second space for providing wiring between the internal logic circuit area and the input/output cells of the outside input/output cell group is provided.

2. A semiconductor integrated circuit device according to claim 1, wherein a blank cell having second guard bands each comprising only a diffusion layer is disposed in the first space, and wherein guard rings for the internal logic circuit area are formed by the first guard bands of the inside input/output cell group and the second guard bands.

3. A semiconductor integrated circuit device according to claim 1, wherein third guard bands are disposed on an internal logic circuit area side of the bonding pad in each of the input/output cells of the outside input/output cell group.

4. A semiconductor integrated circuit device according to claim 3, wherein a fourth guard band is provided on an opposite side to the internal logic circuit area side of the bonding pad in each of the input/output cells of the inside input/output cell group.

5. A semiconductor integrated circuit device according to claim 4, wherein said fourth guard band is formed so as to surround the bonding pad.

6. A semiconductor integrated circuit device according to claim 2, wherein third guard bands are disposed on an internal logic circuit area side of the bonding pad in each of the input/output cells of the outside input/output cell group.

7. A semiconductor integrated circuit device according to claim 6, wherein a fourth guard band is provided on an opposite side to the internal logic circuit area side of the bonding pad in each of the input/output cells of the inside input/output cell group.

8. A semiconductor integrated circuit device according to claim 7, wherein said fourth guard band is formed so as to surround the bonding pad.