Non-volatile and memory fabricated using a dynamic memory process and method therefor

• US 6,222,216 B1
• Filed: 10/21/1997
• Issued: 04/24/2001
• Est. Priority Date: 10/21/1997
• Status: Expired due to Term

• Current Assignee: Foothills IP LLC
• Original Assignee: Silicon Aquarius Incorporated (NewMarket Technology, Inc.)
• Inventors: Rao, G. R. Mohan, Holland, Wayland Bart
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Warren, Matthew E.
• Application Number:
  US08/955,045
• Time in Patent Office: 1,281 Days
• Field of Search: 257/296, 257/298, 257/300, 257/311, 257/68, 257/71, 257/305, 257/306, 257/308
• US Class Current: 257/296
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data processing system having a DRAM and a non-volatile memory, such as a ROM or a programmable ROM (PROM), is implemented on a single integrated circuit using DRAM data processing techniques. The DRAM is manufactured in accordance with known processing techniques. The non-volatile memory is manufactured using the same DRAM manufacturing techniques, with the addition of a processing step in which a first terminal of a stacked capacitor manufactured in accordance with the DRAM process, is coupled to a known-reference voltage. This stacked capacitor structure may be coupled to a known conductor through the formation of a via and the subsequent coupling of a conductor to the stacked capacitor structure through the via. Alternatively, the stacked capacitor structure may be coupled to the known reference voltage through an internal connection to that reference voltage. By using such methodologies, a data processing system is implemented having a DRAM and a non-volatile memory on a single integrated circuit using a same process methodology.

Claims

1. A processing system disposed on a single integrated circuit chip comprising:

a dynamic random access memory disposed within a preselected memory space; and

a read-only memory disposed within said preselected memory space, said read-only memory comprising a plurality of read-only memory cells each including a dynamic random access memory cell including a storage capacitor having first and second plates shorted together and coupled to a preselected fixed voltage.

2. The processing system of claim 1 wherein said system maintains a single copy of an operating system in said memory space.

3. The processing system of claim 2 wherein said operating system is stored exclusively within said read-only memory.

4. The processing system of claim 1 wherein said preselected voltage comprises a high voltage rail.

5. The processing system of claim 1 wherein said preselected voltage comprises a low voltage rail.

6. The processing system of claim 4 wherein said high voltage rail programs a logic one.

7. The processing system of claim 5 wherein said low voltage rail programs a logic zero.

10. The processing system of claim 5 wherein said second conductive layer of said selected cells is coupled to V_SS.

8. A single chip processing system comprising:

an array of rows and columns of memory cells, each row associated with a conductive wordline and each column associated with a conductive bitline, said memory cells each comprising;

a first capacitor conductor;

a second capacitor conductor spaced from said first conductor by a layer of dielectic; and

a transistor selectively coupling said first conductor to a corresponding one of said bitlines in response to a voltage applied to a corresponding one of said wordlines; and

wherein selected ones of said cells further comprise an electrical connection between said first and second conductors thereby programming said selected cells as read-only memory cells.

9. The processing system of claim 8 wherein said second conductive layer of said selected cells is coupled to V_CC.

11. The processing system of claim 8 wherein said read-only memory cells store an operating system.

12. A processing system fabricated on a single integrated circuit chip comprising;

a memory array comprised of a plurality of rows and columns of dynamic random access memory cells each including a pass transistor and a storage capacitor having first and second plates; and

wherein said plates of said capacitors of selected ones of said cells are coupled together and to a preselected voltage to form a read-only memory storing an operating system for said processing system.