Memory cell with self-aligned floating gate and separate select gate, and fabrication process

• US 6,222,227 B1
• Filed: 08/09/1999
• Issued: 04/24/2001
• Est. Priority Date: 08/09/1999
• Status: Expired due to Term

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Actrans System Inc (Microchip Technology Incorporated)
• Inventors: Chen, Chiou-Feng
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/370,557
• Time in Patent Office: 624 Days
• Field of Search: 365/185.01, 365/185.05, 365/185.17, 365/185.18, 365/185.26, 365/185.28, 365/185.29, 365/185.33, 257/316
• US Class Current: 257/316
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Memory cell having a floating gate with lateral edges which are aligned directly above edges of the active area in the substrate, a control gate positioned directly above the floating gate, and a select gate spaced laterally from the control gate. The floating gate has a bottom wall and side walls which face corresponding walls of the control gate in capacitive coupling relationship, with the height of the side walls being on the order of 80 to 160 percent of the width of the bottom wall. In some embodiments, the floating gate is wider than the overlying control gate and has projecting portions which overlie the source and drain regions of the stack transistor. The memory cell is fabricated by forming a poly-1 layer and an overlying dielectric film on a substrate in areas in which the stack transistors are to be formed, forming a poly-2 layer over the dielectric film and over areas of the substrate in which the select transistors are to be formed, patterning the poly-2 layer to form control gates for the stack transistors and select gates for the select transistors, removing the poly-1 layer and the dielectric film to form floating gates in areas which are not covered by the control gates, and forming source and drain regions in the substrate. The floating gates are aligned with active areas in the substrate by forming isolation oxide regions which extend above the substrate at the edges of the active areas, and forming the floating gates on the sides of the isolation oxide regions in alignment with the edges of the active areas.

Claims

1. In a memory cell:

a substrate having an active area with source and drain regions on opposite sides of the active area, a floating gate which overlies the active area with portions of the floating gate extending laterally beyond the active area and overlying portions of the source and drain regions, a control gate positioned directly above the floating gate, and a select gate positioned entirely to one side of the floating gate and the control gate.

2. The memory cell of claim 1 wherein the floating gate has a bottom wall and side walls which face corresponding walls of the control gate in capacitive coupling relationship, with the height of the side walls being on the order of 80 to 160 percent of the width of the bottom wall.

3. The memory cell of claim 2 wherein the bottom wall and the side walls of the floating gate have a thickness no greater than about 1000 Å

.

4. The memory cell of claim 1 wherein the floating gate is wider than the control gate.

5. The memory cell of claim 1 wherein an erase window is formed between the source region and the portion of the floating gate which overlies it.

6. The memory cell of claim 1 wherein the source region has a greater junction depth than the drain region.

7. The memory cell of claim 1 wherein the control gate, the select gate and the source and drain regions are biased to establish a Fowler-Nordheim tunneling path from the floating gate to the source region during an erase operation.

8. The memory cell of claim 1 wherein the control gate, the select gate and the source and drain regions are biased to establish a Fowler-Nordheim tunneling path from the floating gate to the drain region during an erase operation.

9. The memory cell of claim 1 wherein the control gate, the select gate and the source and drain regions are biased to establish a Fowler-Nordheim tunneling path from the source region to the floating gate during a programming operation.

10. The memory cell of claim 1 wherein the control gate, the select gate and the source and drain regions are biased to establish a Fowler-Nordheim tunneling path from the drain region to the floating gate during a programming operation.

11. The memory cell of claim 1 wherein the control gate, the select gate and the source and drain regions are biased to establish hot carrier injection from the active region to the floating gate during a programming operation.

12. In a process of fabricating a memory cell, the steps of:

forming an active area in a substrate, forming a floating gate which overlies the active area with portions of the floating gate extending laterally beyond the active area, forming a control gate directly above the floating gate, forming a select gate entirely to one side of the floating gate and the control gate, and forming source and drain regions on opposite sides of the active area with the laterally extending portions of the floating gate overlying portions of the source and drain regions.

13. The process of claim 12 wherein the floating gate is formed with a bottom wall and side walls which face corresponding walls of the control gate in capacitive coupling relationship, with the height of the side walls being on the order of 80 to 160 percent of the width of the bottom wall.

14. The process of claim 13 wherein the bottom wall and the side walls of the floating gate are formed with a thickness no greater than about 1000 Å

.

15. The process of claim 12 wherein the floating gate is formed wider than the control gate.

16. The process of claim 12 wherein an erase window is formed between the source region and the portion of the floating gate which overlies it.

17. The process of claim 12 wherein the source region is formed with a greater junction depth than the drain region.

18. The process of claim 12, including the steps of biasing the control gate, the select gate and the source and drain regions to establish a Fowler-Nordheim tunneling path from the floating gate to the source region during an erase operation.

19. The process of claim 12, including the steps of biasing the control gate, the select gate and the source and drain regions to establish a Fowler-Nordheim tunneling path from the floating gate to the drain region during an erase operation.

20. The process of claim 12, including the steps of biasing the control gate, the select gate and the source and drain regions to establish a Fowler-Nordheim tunneling path from the source region to the floating gate during a programming operation.

21. The process of claim 12, including the steps of biasing the control gate, the select gate and the source and drain regions to establish a Fowler-Nordheim tunneling path from the drain region to the floating gate during a programming operation.

22. The process of claim 12, including the steps of biasing the control gate, the select gate and the source and drain regions to establish hot carrier injection from the active region to the floating gate during a programming operation.

23. In a memory cell:

a substrate having an active area with source and drain regions of different junction depth on opposite sides of the active area, a floating gate which overlies the active area with portions of the floating gate extending laterally beyond the active area and overlying portions of the source and drain regions, a control gate positioned directly above the floating gate, a select gate positioned to one side of the floating gate and the control gate, and additional source and drain regions formed in the substrate toward opposite sides of the select gate.

24. The memory cell of claim 23 wherein the source region has a greater junction depth than the drain region.

25. In a process of fabricating a memory cell, the steps of:

forming an active area in a substrate, forming a floating gate which overlies the active area with portions of the floating gate extending laterally beyond the active area, forming a control gate directly above the floating gate, forming a select gate entirely to one side of the floating gate and the control gate, forming source and drain regions of different junction depth on opposite sides of the active area with the laterally extending portions of the floating gate overlying portions of the source and drain regions, and forming additional source and drain regions in the substrate toward opposite sides of the select gate.

26. The process of claim 25 wherein the source region is formed to a greater junction depth than the drain region.

27. In a memory cell:

a substrate;

a stack transistor formed on the substrate, comprising an active area in the substrate with source and drain regions on opposite sides of the active area, a floating gate which overlies the active area with portions of the floating gate extending laterally beyond the active area and overlying portions of the source and drain regions, and a control gate positioned directly above the floating gate; and

a select transistor formed on the substrate to one side of the stack transistor, comprising a select gate positioned entirely to the side of the stack transistor, and additional source and drain regions formed in the substrate toward opposite sides of the select gate.

28. The memory cell of claim 27 wherein the source region in the stack transistor has a greater junction depth than the drain region.