Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability

• US 6,222,229 B1
• Filed: 06/14/1999
• Issued: 04/24/2001
• Est. Priority Date: 02/18/1999
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Hebert, Francois, Ng, Szehim
• Primary Examiner(s): Lee, Eddie C.
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/333,123
• Time in Patent Office: 680 Days
• Field of Search: 257/327, 257/328, 257/329, 257/365, 257/275, 257/336, 257/344, 257/320, 257/664, 257/340, 257/488
• US Class Current: 257/327
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A high frequency power field effect transistor has a self-aligned gate-drain shield adjacent to the gate and overlying the drain. Fabrication of the structure does not require complex or costly processing and the resulting self-aligned shield structure minimizes increase to input and output capacitances. Hot carrier injection and related shifts are reduced thereby improving reliability of the transistor.

Claims

1. A field effect transistor having reduced gate to drain capacitance comprising:

a semiconductor body having a major surface,

a source region of first conductivity-type abutting said surface,

a drain region of said first conductivity-type abutting said surface and spaced from said source region by a channel,

a gate overlying said channel and part of said drain and insulated therefrom by a dielectric material, and

a gate/drain shield between the gate and drain aligned with and spaced from said gate with no overlap of the gate on the shield and overlying said drain and insulated therefrom.

2. The field effect transistor as defined by claim 1 wherein said shield plate comprises a conductor selected from the group consisting of polysilicon, polycide, silicide, salicide, and refractory metals.

3. The field effect transistor as defined by claim 1 wherein said field effect transistor comprises a lateral field effect transistor.

4. The field effect transistor as defined by claim 1 wherein said field effect transistor comprises an extended drain field effect transistor.

5. The field effect transistor as defined by claim 1 wherein said shield plate includes a contact for electrically biasing the shield plate.

6. The field effect transistor as defined by claim 1 wherein said device comprises a RF power amplifier.

7. The field effect transistor as defined by claim 5 wherein said field effect transistor comprises a lateral field effect transistor.

8. The field effect transistor as defined by claim 5 wherein said field effect transistor comprises an extended drain field effect transistor.

9. The field effect transistor as defined by claim 5 wherein said shield plate is coupled to an AC ground.

10. The field effect transistor as defined by claim 8 wherein said shield plate is connected to a DC voltage potential.

11. The field effect transistor as defined by claim 5 wherein said shield plate is connected to a DC voltage potential.