Method of making an elevated source/drain with enhanced graded sidewalls for transistor scaling integrated with spacer formation

• US 6,222,230 B1
• Filed: 12/03/1998
• Issued: 04/24/2001
• Est. Priority Date: 12/03/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gardner, Mark I., May, Charles E., Fulford, H. Jim
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US09/204,967
• Time in Patent Office: 873 Days
• Field of Search: 257/329, 257/330, 257/333
• US Class Current: 257/329
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas of the substrate. Each of the transistors has a doped region positioned in the substrate, an insulating layer positioned in a tapered trench in the substrate that extends through and sub-divides the doped region into a first source/drain region and a second source/drain region. The insulating layer is channel-shaped with a base, a first upwardly sloping sidewall and a second upwardly sloping sidewall. A gate electrode is positioned on the insulating layer. The channel-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate. The sloped sidewalls double as spacers, enabling process simplification.

Claims

1. An integrated circuit, comprising:

a substrate; and

a plurality of transistors positioned on a plurality of active areas of the substrate, each of the transistors hang a doped region positioned in the substrate, a first insulating layer positioned in a tapered trench in the substrate that extends through and sub-divides the doped region into a first source/drain region and a second source/drain region, the first insulating layer having a base, a first upwardly sloping sidewall having a first upper surface and a second upwardly sloping sidewall having a upper surface, a gate electrode positioned on the insulating layer and having first and second side surfaces projecting above the substrate, and a second insulating layer positioned on the substrate adjacent to the first and second side surfaces of the gate electrode and covering the first and second upper surfaces of the first insulating layer.

2. The integrated circuit of claim 1, wherein the substrate has a horizontal plane, the first and second sidewalls projecting upwardly at an angle of about 10°

to 80°

with respect to the horizontal plane.

3. The integrated circuit of claim 1, wherein the base has a first thickness, the first upwardly projecting sidewall has a second thickness and the second upwardly projecting has a third thickness, the second and third thicknesses being larger than the first thickness.

4. The integrated circuit of claim 1, wherein the first insulating layer comprises silicon dioxide.

5. The integrated circuit of claim 1, wherein the first insulating layer comprises a first layer of insulating material positioned on a second layer of insulating material.

6. The integrated circuit of claim 1, wherein the second insulating layer has an upper surface that is substantially planar with the gate electrode.

7. A transistor, comprising:

a substrate;

a first source/drain region positioned in the substrate and a second source/drain region positioned in the substrate and separated from the first source/drain region by a tapered trench;

a first insulating layer positioned in the tapered trench, the first insulating layer having a base, a first upwardly sloping sidewall having a first upper surface and a second upwardly sloping sidewall having a second upper surface;

a gate electrode positioned on the first insulating layer and having first and second side surfaces projecting above the substrate; and

a second insulating layer positioned on the substrate adjacent to the first and second side surfaces of the gate electrode and covering the first and second upper surfaces of the first insulating layer.

8. The transistor of claim 7, wherein the substrate has a horizontal plane, the first and second sidewalls projecting upwardly at an angle of about 10°

to 80°

with respect to the horizontal plane.

9. The transistor of claim 7, wherein the base has a first thickness, the first upwardly projecting sidewall has a second thickness and the second upwardly projecting sidewall has a third thickness, the second and third thicknesses being larger than the first thickness.

10. The transistor of claim 7, wherein the first insulating layer comprises silicon dioxide.

11. The transistor of claim 7, wherein the first insulating layer comprises a first layer of insulating material positioned on a second layer of insulating material.

12. The transistor of claim 7, wherein the second insulating layer has an upper surface that is substantially planar with the gate electrode.