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High speed parallel/serial link for data communication

  • US 6,222,380 B1
  • Filed: 06/11/1999
  • Issued: 04/24/2001
  • Est. Priority Date: 06/15/1998
  • Status: Expired due to Term
First Claim
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1. An interface comprising:

  • a plurality of latches that store a subset of a group of parallel bits;

    a system clock running at a predetermined speed that gates the bits into the plurality of latches;

    a multiplexer circuit, responsive to a control signal, that selects stored bits to generate a serial bit stream;

    a latch that receives the serial bit stream;

    a clock signal operating at N times the speed of the system clock operatively coupled to the latch; and

    a low power/impedance matching differential drive circuit that receives the serial bit stream from said latch and generates differential signals, with relatively high peak-to-peak signal swings.

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