High speed parallel/serial link for data communication

• US 6,222,380 B1
• Filed: 06/11/1999
• Issued: 04/24/2001
• Est. Priority Date: 06/15/1998
• Status: Expired due to Term

• Current Assignee: MediaTek, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Marshall, John, Gerowitz, Robert Glen, Gray, Carl Thomas, Rizzo, Raymond Paul, Riedle, Christopher G.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/330,968
• Time in Patent Office: 683 Days
• Field of Search: 326/30, 326/37, 326/38, 326/82, 326/83, 326/86
• US Class Current: 326/38
• CPC Class Codes: C22C 21/08 with silicon
• CPC Class Codes: C22F 1/047 of alloys with magnesium as the next major constituent
• CPC Class Codes: C22F 1/05 of alloys of the Al-Si-Mg type, i.e. containing silicon and magnesium in approximately equal proportions
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

An interface system that conveys data at approximately 500 MBitsps between modules. The interface system performs multistream serialization at the transmitter and multistream de-serialization at the Receiver. As a consequence, fewer interface connections are required between the modules.

Claims

1. An interface comprising:

a plurality of latches that store a subset of a group of parallel bits;

a system clock running at a predetermined speed that gates the bits into the plurality of latches;

a multiplexer circuit, responsive to a control signal, that selects stored bits to generate a serial bit stream;

a latch that receives the serial bit stream;

a clock signal operating at N times the speed of the system clock operatively coupled to the latch; and

a low power/impedance matching differential drive circuit that receives the serial bit stream from said latch and generates differential signals, with relatively high peak-to-peak signal swings.

2. The interface of claim 1 wherein N, the speed of the clock signal, is approximately four times the speed of the system clock.

3. The interface system of claim 1 further including a receiver that receives differential signals and converts them to single ended signals at a predetermined voltage level;

a first circuit arrangement including delay elements that delay the signals and an algorithm that parses the signal to select strobe points for bit recovery; and

a second circuit arrangement including an algorithm that uses the bit recovery information to reconstruct the subset of a group of parallel bits.

4. The interface of claim 3 wherein the subset includes a nibble (4 bits).

25. The apparatus in claims 1 or 17 further including:

at least one receiver that receives a predetermined bit pattern;

a storage that stores the predetermined bit pattern;

a controller that parses the predetermined bit pattern to generate a mask which is used to identify bit recovery points that are subsequently used to recover data bits from subsequently received data signals.

5. An interface system comprising:

at least one circuit arrangement partitioning parallel bits into subsets of parallel bits;

a plurality of latches that store a subset of the parallel bits;

a system clock operating at a predetermined speed that gates the bits into the latches;

a multiplexer circuit, responsive to a control signal, that selects stored bits to generate a serial bit stream;

a latch that receives the serial bit stream;

a clock signal N times the speed of the system clock operatively coupled to the latch; and

a low power/impedance matching differential drive circuit that receives the serial bit stream from the latch and generates differential signals with relatively high peak-to-peak signal swings.

6. The interface system of claim 5 further including a plurality of transmission links wherein each one of the plurality of transmission links is operatively coupled to transmit data from a low power/impedance matching differential drive circuit.

7. The interface system of claim 6 further including:

a plurality of receivers one of each operatively coupled and dedicated to receive differential signals from one of the transmission links, process the differential signals and provide a single ended signal at a desired voltage level; and

circuit arrangement that uses the single ended signal to reconstruct the parallel data bits.

8. The interface system of claim 5 further including a module having multiple integrated circuits thereon and a parallel interface having a plurality of parallel output lines operatively coupled to the at least one circuit arrangements.

9. The interface system of claim 8 further including circuit including conducting wires that partition the parallel interface.

10. The interface system of claim 9 further including:

a plurality of receivers one of each operatively coupled and dedicated to receive differential signals from one of a plurality of transmission links, process the differential signals and provide a single ended signal at a desired voltage level; and

circuit arrangement that uses the single ended signal representative of the training pattern to establish receiver synchronization prior to processing data to reconstruct parallel data bits.

11. The interface system of claim 10 further including a module having multiple integrated circuits thereon and a parallel interface operatively coupled to conductors carrying the parallel data bits.

12. The interface system of claim 5 wherein N=4.

13. A method for transmitting data comprising the steps of:

partitioning the data into multiple groups of N parallel streams;

generating one serial bit stream for each group of N parallel bit streams;

providing a plurality of serial links;

transmitting simultaneously each group of parallel bit streams over a different one of the plurality of said serial links; and

transmitting, on at least one of the plurality of said serial links, training pattern of N-bits transition rich sequence prior to transmitting data on the at least one of the plurality of said serial links.

14. The method of claim 13 wherein N includes an even integer.

15. The method of claim 13 wherein N=4.

16. The method of claim 13 wherein the N-bits transition rich sequence further includes 7 Hex “

A”

(1 0 1

     0) patterns and 1 Hex “

5”

(0 1 0

     1) pattern.

17. A system for transmitting data comprising:

a multiplexer that partitions the data into multiple groups of N parallel bit streams;

a converter that converts each one of the multiple groups of N parallel bit streams into one serial bit stream;

a plurality of serial links wherein each one of the serial link transmits one of the serial bit stream containing the N parallel bit streams; and

a pattern generator that generates a predetermined training pattern which is transmitted through at least one of the plurality of serial links prior to transmitting data through said at least one of the plurality of serial links.

18. An interface arrangement comprising:

a plurality of latches that receives a subset of parallel bits from a group of parallel bits;

a multiplexer circuit arrangement, response to a control signal, to generate a serial bit stream from the subset of parallel bits;

a differential driver circuit responsive to the serial bit streams to generate differential signals to be transmitted via communications links; and

a pattern generator that generates a training pattern that is transmitted by the communications links prior to transmitting the subset of parallel bits there through.

19. The interface arrangement of claim 18 wherein the training pattern includes N-bits transition rich sequence.

20. The interface arrangement of claim 19 wherein the N-bit transition rich sequence further includes 7 Hex “

A”

(1 0 1

     0) patterns and 1 Hex “

5”

(0 1 0

     1) pattern.

21. The interface arrangement of claim 18 or 20 further including a latch that receives the serial bit data stream from the multiplexer circuit;

and

a clock signal that drives the latch to output serial data at a rate N times greater than the rate at which the serial data stream was received by the latch.

22. The interface arrangement of claim 21 wherein N=4.

23. The interface arrangement of claim 18 or 20 further including a receiver that receives differential signals which are converted to single ended signals at a predetermined voltage level;

a first circuit arrangement including delay elements that delay data in the single ended signals;

a controller that parses the data to select bit recovery strobe points; and

a second circuit arrangement responsive to control signals, provided by the controller and bits recovered at the strobe points to reconstruct the subset of parallel bits.

24. The interface arrangement of claim 23 wherein the receiver further includes a third circuit arrangement that monitors the input to the receiver and generates a “

loss of signal”

indication if the inputs to the receiver are not coupled to the differential driver.