Level shifter circuit

• US 6,222,384 B1
• Filed: 10/05/1998
• Issued: 04/24/2001
• Est. Priority Date: 10/10/1997
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Kim, Kyung-Wol
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/166,224
• Time in Patent Office: 932 Days
• Field of Search: 326/81, 326/80, 326/82, 326/83, 326/68, 326/59, 326/60, 365/189.11
• US Class Current: 326/68
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A level shifter circuit of the preferred embodiment can be used as a transfer gate driver of a memory circuit such as a DRAM. A pair of cross-coupled transistors receives a first potential. A plurality of transistors are coupled between the pair of cross-coupled transistors and a second potential. An output unit has a pull-down switch for providing an output signal of one of first, second and third potentials and are coupled to the pair of cross-coupled transistor and the plurality of transistors. The third potential has a potential between the first and second potentials.

Claims

1. A level shifter circuit, comprising:

an inverter for inverting an input signal;

a first transistor having a gate to receive an input signal inverted by the inverter, a source coupled to a ground voltage, and a drain coupled to a first node;

a second transistor having a gate to receive a first input signal, a source coupled to a ground voltage, and a drain coupled to a second node;

a third transistor having a gate to receive an externally applied voltage, a source coupled to the second node, and a drain coupled to a third node;

a fourth transistor having a gate coupled to the third node, and a drain coupled to a fourth node, wherein a source and a substrate receives a raised voltage;

a fifth transistor having a gate coupled to the fourth node, and a drain coupled to the third node, wherein a source and a substrate receives the raised voltage;

a sixth transistor having a gate coupled to the fourth node, and a drain coupled to a fifth node wherein a source and a substrate receive the raised voltage;

a seventh transistor having a gate coupled to the fourth node, a drain coupled to the fifth node, and a source for receiving a second input signal;

an eighth transistor having a gate coupled to the third node, a source coupled to the fifth node, and a drain coupled to receive the second input signal; and

a ninth transistor having a gate to receive an externally applied voltage, a source coupled to the first node, and a drain coupled to a fourth node.

2. The level shifter circuit of claim 1, wherein the input signal is directly outputted irrespective of the level of the second input signal by using a CMOS pull-down switch.

3. The level shifter circuit of claim 1, wherein one of the ground voltage, raised voltage and externally applied voltage is provided as an output signal at the fifth node.

4. The level shifter circuit of claim 1, wherein said first, second, third and seventh transistors are NMOS transistors, and said fourth, fifth,, sixth and eighth transistors are PMOS transistors.

5. A level shifter comprising:

a pair of cross-coupled transistors coupled for receiving a first potential;

a plurality of transistors coupled between said pair of cross-coupled transistors and a second potential; and

an output unit having a pull-down switch for providing an output signal of one of first, second and third potentials and coupled to said pair of cross-coupled transistor and said plurality of transistors, the third potential having a potential between the first and second potentials, wherein said plurality of transistors includes a first transistor coupled between the second potential and a first node, a second transistor coupled between the second potential and a second node, a third transistor coupled between the cross-coupled transistors and the first node, and a fourth transistor coupled between the cross-coupled transistors and the second node.

6. The level shifter of claim 5, wherein each of said first, second, third and fourth transistors includes first and second electrodes and a control electrode, the first and second electrodes of said first and third transistors, respectively, being coupled to the first node, and first and second electrodes of said second and fourth transistors, respectively, being coupled to the second node, and the control electrodes of first and second transistors being coupled for receiving a first input signal and an inverted first input signal and control electrodes of said third and fourth transistors being coupled for receiving the third potential.

7. The level shifter of claim 6, wherein said first, second, third and fourth transistors are NMOS transistors.

8. The level shifter of claim 5, wherein said cross-coupled transistor comprises:

a fifth transistor having first and second electrodes and a control electrode;

a sixth transistor having first and second electrodes and a control electrode, the first electrode and a substrate of said fifth and sixth transistors being coupled to receive the first potential, the control electrode of said fifth transistor being coupled to the second electrode of the sixth transistor and the control electrode of said sixth transistor being coupled to the second electrode of the fifth transistor, wherein the second electrode of said fifth and sixth transistors is coupled to corresponding transistor of said plurality of transistors.

9. The level shifter of claim 8, wherein fifth and sixth transistors are PMOS transistors.

10. The level shifter of claim 5, wherein said output unit further comprises a fifth transistor coupled between the first potential and said pull-down switch.

11. The level shifter of claim 10, wherein said pull-down switch comprises sixth and seventh transistors, each of said fifth, sixth and seventh transistors having first and second electrodes and a control electrode, the control electrode of fifth, sixth and seventh transistors being coupled to said cross-coupled transistors and the plurality of transistors, the first electrodes of the fifth transistor and substrate of fifth and seventh transistors being coupled to the first potential, the second electrode of said fifth and sixth transistors and the first electrode of said seventh transistor being coupled to an output node for providing the output signal, and the first electrode of the sixth transistor and the second electrode of the seventh transistor being coupled to receive a second input signal.

12. The level shifter of claim 11, wherein said fifth and seventh transistors are PMOS transistors and said sixth transistor is an NMOS transistor.

13. A level shifter comprising:

a pair of cross-coupled transistors coupled for receiving a first potential;

a plurality of transistors coupled between said pair of cross-coupled transistors and a second potential; and

an output unit having a pull-down switch for providing an output signal of one of first, second and third potentials and coupled to said pair of cross-coupled transistor and said plurality of transistors, the third potential having a potential between the first and second potentials, wherein said output unit further includes a first transistor coupled between the first potential and said pull-down switch, second and third transistors, each of said first, second and third transistors having first and second electrodes and a control electrode, the control electrode of first, second and third transistors being coupled to said cross-coupled transistors and the plurality of transistors, the first electrodes of the first transistor and substrate of first and third transistors being coupled to the first potential, the second electrode of said first and second transistors and the first electrode of said third transistor being coupled to an output node for providing the output signal, and the first electrode of the second transistor and the second electrode of the third transistor being coupled to receive a second input signal.