Low voltage differential driver with multiple drive strengths

• US 6,222,388 B1
• Filed: 03/17/1999
• Issued: 04/24/2001
• Est. Priority Date: 04/18/1997
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Bridgewater, Jr., Walter Francis
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/270,947
• Time in Patent Office: 769 Days
• Field of Search: 326/83, 326/86, 326/57, 326/58, 327/108
• US Class Current: 326/86
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/018514 with at least one differential stage H03K19/018528 and H03K19/018542 take precedence

Abstract

The first pulse problem for a low-voltage differential SCSI bus driver is remedied by supplying greater power for a first pulse of a bus line after a steady state condition. Activity detection circuitry detects when a signal has remained in a steady state for a number of bus cycles and enables an additional power boosting differential driver to deliver an appropriate amount of power for a limited amount of time in order to produce a quality first pulse while minimizing power output. The extra power needed to remedy the quality of the first pulse is only supplied for the duration of the first pulse so that the output driver strength is minimized and the total power over time that an integrated circuit must dissipate is reduced. In another embodiment, instead of greater than normal power being delivered for a first pulse, the output driver is decreased in its output drive strength while an output remains in a particular state. When the output does finally switch states, it switches at normal strength; the net effect is an increased drive strength from the steady state to the new state. Step down control circuitry is used to determine after a specified number of clock pulses how much power should be stepped down and in how many increments.

Claims

1. A low-voltage differential driver for use in transmitting an output value on a bus line of a computer system having a system clock, said driver comprising:

a step down control circuit including logic circuitry that determines a state of said output value and enabling circuitry that produces a power reduce signal while said output value remains in a steady state and before a first pulse of said output value is to be transmitted;

a differential driver circuit arranged to deliver varying levels of power to a pair of differential signals used for transmitting said output value over said bus line of said computer system;

a first current source circuit that is arranged to supply varying levels of current to said differential driver circuit; and

a second current source circuit that is arranged to supply varying levels of current to said differential driver circuit, said first current source circuit and said second current source circuit being arranged to receive said power reduce signal and to reduce a level of current supplied to said differential driver circuit when said power reduce signal is active, and being further arranged to deliver a normal level of current when said power reduce signal is not active, whereby said first pulse of said output value receives a greater power level than a power level delivered to said output value before said first pulse.

2. A low-voltage differential driver as recited in claim 1 wherein said bus line is part of a small computer system interface (SCSI) bus that is terminated with no bias voltage, and wherein said differential driver circuit supplies power to drive said pair of differential signals over said SCSI bus.

3. A low-voltage differential driver as recited in claim 1 wherein said differential driver circuit supplies said greater power level for only a first pulse of said output value after said output value has remained in one state for a specified number of system clock cycles, whereby said first pulse is of a sufficient amplitude to be accurately detected by a receiver of said computer system and whereby power of said driver is conserved.

4. A low-voltage differential driver as recited in claim 1 wherein said logic circuitry of said step down control circuit is arranged to detect a state of a data output value, and said enabling circuitry of said step down control circuit produces said power reduce signal upon reaching a specified count of a number of system clock cycles during which said state of said data output value has remained constant, whereby said first pulse of said data output value is increased in amplitude.

5. A low-voltage differential driver as recited in claim 4 wherein said enabling circuitry of said step down control circuit produces a plurality of power reduce signals, each of said power reduce signals being produced upon reaching a distinct specified count of a number of system clock cycles during which said state of said data output value has remained constant, and wherein said first current source circuit and said second current source circuit being further arranged to receive said power reduce signals and to incrementally reduce a level of current supplied to said differential driver circuit upon receipt of each of said power reduce signals.

6. An integrated circuit including the driver as recited in claim 1.

7. A method of transmitting an output value on a bus line of a computer system having a system clock using a low-voltage differential driver, said method comprising the steps of:

determining whether said output value has remained in a constant state for a specified number of system clock cycles;

producing a power reduce signal when it is determined that said output value has remained in said constant state for a specified number of system clock cycles and before a first pulse of said output value is to be transmitted;

reducing a level of current supplied to a differential driver circuit used for transmitting said output value over said bus line of said computer system, such that said output value is transmitted in said constant state at a reduced power level;

determining whether said output value has changed state;

disabling said power reduce signal when it is determined that said output value has changed state; and

supplying a normal level of current to said differential driver circuit, whereby said first pulse of said output value receives a greater power level than said reduced power level delivered to said output value before said first pulse.

8. A method as recited in claim 7 wherein said bus line is part of a small computer system interface (SCSI) bus that is terminated with no bias voltage, and wherein said reduced power level and said greater power level drive a pair of differential signals over said SCSI bus.

9. A method as recited in claim 7 wherein said step of supplying a normal level of current supplies said greater power level for only a first pulse of said output value after said output value has remained in said constant state for a specified number of system clock cycles, whereby said first pulse is of a sufficient amplitude to be accurately detected by a receiver of said computer system and whereby power of said driver is conserved.

10. A method as recited in claim 7 wherein said step of producing a power reduce signal includes the sub-step of producing a plurality of power reduce signals, each of said power reduce signals being produced upon reaching a distinct specified count of a number of system clock cycles during which said state of said output value has remained constant, and wherein said step of reducing a level of current includes the sub-step of receiving said power reduce signals and incrementally reducing a level of current supplied to said differential driver circuit upon receipt of each of said power reduce signals.