AC plasma gas discharge gray scale graphics, including color, and video display drive system

• US 6,222,511 B1
• Filed: 01/12/1998
• Issued: 04/24/2001
• Est. Priority Date: 12/17/1990
• Status: Expired due to Fees

• Current Assignee: Feldman Technologies Corporation
• Original Assignee: Photonic Systems Inc. (Photonics Systems Holding GmbH)
• Inventors: Stalker, Michael B., Stoller, Ray A.
• Primary Examiner(s): NGUYEN, CHANH DUY
• Application Number:
  US09/003,937
• Time in Patent Office: 1,198 Days
• Field of Search: 345/60, 345/61, 345/62, 345/63, 345/64, 345/65, 345/77, 345/41, 315/169.1, 315/169.3, 315/169.4
• US Class Current: 345/60
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/293 for address discharge
• CPC Class Codes: G09G 3/294 for lighting or sustain discharge
• CPC Class Codes: G09G 3/296 Driving circuits for producing the waveforms applied to the driving electrodes
• CPC Class Codes: G09G 3/297 using opposed discharge type panels
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A drive system is shown for AC plasma (ACP) gas discharge flat bistable matrix panels on which real-time video and computer graphics, both with pixel by pixel gray scale are displayed. The drive scheme increases scan speed, reduces complexity, and minimizes the circuitry required to operate the video and computer graphics on the ACP display by a unique application of standard high density memory IC architecture and panel drive waveform technique applying all of the drive voltages to the ACP panel from the row (Y) axis and only selective cancellation voltage from the column (x) axis.

Claims

1. A drive system for an AC plasma display panel having pixel elements located by column (X) and row (Y) electrodes, X electrode driver means connected to the X electrodes and Y driver means connected to the Y electrodes and a source of N-bit word signals representing the amplitude of video signals for each pixel element located by the crossing of said X and Y electrodes and means for translating said N-bit word to driver signals for controlling the X and Y driver means to cause each pixel element to selectively emit light, a first voltage driver means connected between the output storage elements and said X electrode for supplying X axis control voltage to said column X electrodes, said first voltage driver means being dedicated solely to high speed pixel control which is logic ground based and a second voltage driver means connected between said output storage elements and said row (Y) electrodes for supplying Y axis control voltages to said row electrodes, said X axis control voltages being applied to said column (X) electrodes at selected times to selectively cancel said Y axis control voltage,

wherein there are write, erase and sustain sequences for said pixels;

and

wherein said second voltage driver means supplies the row (Y) electrodes with all of the drive voltage for the non-selective write, erase, and sustain sequences, while the first voltage driver means applies axis as control voltage only to said column (X) electrodes at selected time to cancel, write or erase the Y axis drive control voltages.

2. The drive system defined in claim 1, wherein said source of N-bit word signals representing the amplitudes of video signals for said pixel elements includes:

a) an interface circuit comprising a digitizer for receiving video signals from one of a selected plurality of video sources and producing, in digital form, pixel data, pixel clock, and horizontal and vertical synchronizing signals to selectively capture and resynchronize video images.

3. The drive system defined in claim 1, wherein said source of N-bit word signals representing the amplitudes of video signals for said pixel elements includes:

a) an interface circuit comprising a digitizer for receiving video signals from one of a selected plurality of video sources and producing, in digital form, pixel data, pixel clock, and horizontal and vertical synchronizing signals to selectively capture and resynchronize video graphics.

4. The drive system defined in claim 1, wherein said source of N-bit word signals representing the amplitudes of video signals for said pixel elements includes:

a) an interface circuit comprising a digitizer for receiving video signals from one of a selected plurality of video sources and producing, in digital form, pixel data, pixel clock, and horizontal and vertical synchronizing signals to selectively capture and resynchronize video images and video graphics.

5. The drive system defined in claim 1, wherein said source of N-bit word signals representing the amplitudes of video signals for said pixel elements includes:

a) an interface circuit comprising a rescan converter for receiving video signals from one of a selected plurality of video sources and producing, in digital form, pixel data, pixel clock, and horizontal and vertical synchronizing signals to selectively capture and resynchronize video images.

6. The drive system defined in claim 1, wherein said source of N-bit word signals representing the amplitudes of video signals for said pixel elements includes:

a) an interface circuit comprising a rescan converter for receiving video signals from one of a selected plurality of video sources and producing, in digital form, pixel data, pixel clock, and horizontal and vertical synchronizing signals to selectively capture and resynchronize video graphics.

7. The drive system defined in claim 1, wherein said source of N-bit word signals representing the amplitudes of video signals for said pixel elements includes:

a) an interface circuit comprising a rescan converter for receiving video signals from one of a selected plurality of video sources and producing, in digital form, pixel data, pixel clock, and horizontal and vertical synchronizing signals to selectively capture and resynchronize video images and video graphics.

8. The drive system defined in claim 1, wherein said source of N-bit word signals representing the amplitudes of video signals for said pixel elements includes:

a) an interface circuit comprising a digitizer and a rescan converter for receiving video signals from one of a selected plurality of video sources and producing, in digital form, pixel data, pixel clock, and horizontal and vertical synchronizing signals to selectively capture and resynchronize video images.

9. The drive system defined in claim 1, wherein said source of N-bit word signals representing the amplitudes of video signals for said pixel elements includes:

a) an interface circuit comprising a digitizer and a rescan converter for receiving video signals from one of a selected plurality of video sources and producing, in digital form, pixel data, pixel clock, and horizontal and vertical synchronizing signals to selectively capture and resynchronize video graphics.

10. The drive system defined in claim 1, wherein said source of N-bit word signals representing the amplitudes of video signals for said pixel elements includes:

a) an interface circuit comprising a digitizer and a rescan converter for receiving video signals from one of a selected plurality of video sources and producing, in digital form, pixel data, pixel clock, and horizontal and vertical synchronizing signals to selectively capture and resynchronize video images and graphics.

11. The drive system defined in claim 1, wherein the connection between said drive system and a source of said video signals is digitized video produced as a stream of N-bit pixel data bites, and associated pixel clock, and horizontal and vertical sychronizing signals.

12. The drive system defined in claim 1, wherein said source may include one or more of the group comprising a computer, camera, VCR, and TV receiver.