Single transistor cell, method for manufacturing the same, memory circuit composed of single transistor cells, and method for driving the same

• US 6,222,756 B1
• Filed: 12/29/1998
• Issued: 04/24/2001
• Est. Priority Date: 12/31/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Lee, Jong-ho
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US09/221,974
• Time in Patent Office: 847 Days
• Field of Search: 365/145, 365/65, 365/63, 257/295
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties

Abstract

A semiconductor memory device, a method for manufacturing the same, a memory circuit including the semiconductor memory device, and a method for driving the same, are provided. In detail, one transistor forms a memory cell, and a single transistor cell capable of arbitrarily accessing the memory cell, a method for manufacturing the same, a memory circuit, and a method for driving the memory circuit, are provided. An island type semiconductor layer as an active region is formed on a ferroelectric layer. A word line crosses the semiconductor layer. A source is formed on the semiconductor layer on one side of the word line, and a drain is formed on the other side. A plate line is formed below the ferroelectric layer to face the word line, and intersects the word line. A drive line is connected to the source, and a bit line is connected to the drain.

Claims

1. A single transistor cell comprising:

a rectangular plate line extending in a first direction;

a rectangular ferroelectric line extending in a second direction perpendicular to the first direction, and formed on the plate line;

an island type semiconductor layer formed on the ferroelectric line in a region where the ferroelectric line and the plate line overlap each other; and

a rectangular word line extending in the second direction, and formed on and across the semiconductor layer.

2. The single transistor cell of claim 1, further comprising:

a drive line connected to the semiconductor layer on a first side of the word line; and

a bit line connected to the semiconductor layer on a second side of the word line.

3. The single transistor cell of claim 2, further comprising:

a source formed on the semiconductor layer on the first side; and

a drain formed on the semiconductor layer on the second side.

4. The single transistor cell of claim 2, wherein the drive line crosses the bit line.

5. The single transistor cell of claim 4, wherein the bit line is positioned above the drive line.

6. The single transistor cell of claim 1, wherein the plate line is formed of platinum, and the ferroelectric line is formed of one selected from the group consisting of PZT, PLZT, PNZT, PbTiO₃ and Y1.

7. The single transistor cell of claim 1, wherein the semiconductor layer is formed of an oxide such as SnO₂.

8. The single transistor cell of claim 1, wherein the word line is formed of a material having a high work function.

9. The single transistor cell of claim 8, wherein the word line is formed of polysilicon doped with impurities or aluminum.

10. The single transistor cell of claim 1, wherein the word line is formed of polysilicon doped with impurities or aluminum.

11. The single transistor cell of claim 1, wherein the ferroelectric line has a planarized surface.

12. The single transistor cell of claim 1, further comprising:

a thin oxide layer formed of Al2O3 by a method such as atomic layer deposition (ALD) between the semiconductor layer and word line.

13. A single transistor cell comprising:

an island type semiconductor layer as an active region formed on a ferroelectric layer;

a word line crossing the semiconductor layer;

a source formed on the semiconductor layer on a first side of of the word line, and a drain formed on the semiconductor layer on a second side of the word line;

a plate line formed below the ferroelectric layer to face the word line, crossing the word line;

a drive line connected to the source; and

a bit line connected to the drain.

14. The single transistor cell of claim 13, wherein the drive line crosses the bit line.