Multi-state memory

• US 6,222,762 B1
• Filed: 08/07/1997
• Issued: 04/24/2001
• Est. Priority Date: 01/14/1992
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Fong, Yupin Kawing, Guterman, Daniel C.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/910,947
• Time in Patent Office: 1,356 Days
• Field of Search: 365/185.01, 365/185.03, 365/185.2, 365/185.22, 365/185.21
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Claims

1. A multi-state memory comprising:

a plurality of EEPROM memory cells, each for storing one of a plurality of multi-states, organized into a plurality of sectors, each sector comprising an array of rows and columns;

cell operating circuitry comprising;

sense circuitry organized in a column oriented manner;

steering elements organized in a column oriented manner; and

select circuitry organized in a row oriented manner,

wherein one or more selected cells along a row are capable of being read simultaneously;

a reference source;

verification circuitry for selected cells for applying to associated steering elements of said selected cells conditions corresponding to verification of corresponding write state and for receiving read data using said reference source for determining if a selected one of said memory cells has been adequately programmed to the conduction characteristics associated with a desired programmed state; and

write circuitry organized in a column oriented manner,

wherein a selected one or more of said memory cells are capable of being written simultaneously with associated steering elements set to corresponding write states, and including termination circuitry for terminating the programming of selected memory cells along said row being programmed when said verification circuitry indicates said selected memory cells have been adequately programmed to their desired states.

2. A memory as in claim 1 wherein said reference comprises an adjustable reference capable of presenting a plurality of reference values, each associated with one of said multi-states.

3. A memory as in claim 2 wherein said reference comprises a stairstep current source.

4. A memory as in claim 1 wherein said reference comprises a plurality of reference values, each associated with one of said multi-states.

5. A memory as in claim 4 wherein each of said reference values comprises a current source.

6. A memory as in claims 2 or 4 wherein said write circuitry operates to write a selected set of cells along a selected row, independently terminating said programming of each of said selected set of cells when said verification circuitry indicates that level of programming has been achieved.

7. A memory as in claim 1 further comprising a memory controller for establishing desired read points for each of a plurality of physical states, based upon said raw data converted to digital form read from each said tracking cell.

8. A memory as in claims 1 or 7 wherein a sector is the smallest erasable unit.

9. A memory as in claims 1 or 7 wherein said memory controller also determines a physical to logical state translation of each sector.

10. A memory as in claims 1 or 7 wherein said memory controller also determines the quality of data read from each cell.

11. A memory as in claims 1 or 7 wherein said tracking cells are read periodically to establish said read compare points.

12. A multi-state memory as in claim 11 wherein said tracking cells are read in the event of a failure in order to establish said read compare points.

13. A memory as in claims 1 or 7 wherein said tracking cells are read as part of normal read operations in order to reestablish said read compare points.

14. A memory as in claims 1 or 7 wherein said raw data comprises memory cell current measurements.

15. A memory as in claims 1 or 7 wherein said compare points are established with an optimum margin established based on the raw data read from said tracking cells.

16. A memory as in claims 1 or 7 wherein said memory controller also establishes poor margin compare points.

17. A multi-state memory as in claim 16 wherein said poor margin compare points are used to provide a measure of the quality of data read from memory cells.

18. A multi-state memory as in claim 17 wherein said memory controller, in response to determining that read data has poor margin, causes said data to be rewritten.

19. A multi-state memory as in claim 18 wherein said rewriting of data is performed on a cell basis if the poor margin read data requires a cell to be moved to a more programmed state.

20. A multi-state memory as in claim 18 wherein said rewriting of data is performed on a sector basis if the poor margin read data requires a cell to be moved to a less programmed state.

21. A multi-state memory as in claim 20 wherein said reprogramming is performed by erasing the sector, and then programming the sector.

22. A memory as in claim 18 which further comprises a counter for maintaining a count of the number of times data is rewritten in response to poor margin and, upon reaching a predetermined count, causes selected ones of said memory cells to be mapped out rather than rewritten.

23. A memory as in claim 22 which comprises one such counter per sector.

24. A memory as in claims 1 or 7 wherein said memory cells and said memory controller are contained on a single integrated circuit.

25. A memory as in claims 1 or 7 wherein said memory cells are contained in one or more integrated circuits, and said memory controller is contained on another integrated circuit.