Nonvolatile semiconductor memory and read method

• US 6,222,763 B1
• Filed: 02/03/2000
• Issued: 04/24/2001
• Est. Priority Date: 12/20/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp, Hitachi Device Engineering Co., Ltd. (Japan Display Incorporated)
• Inventors: Sato, Hiroshi, Miyamoto, Naoki, Kawahara, Takayuki, Harada, Toshinori, Kubono, Shoji
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Tran, M.
• Application Number:
  US09/497,212
• Time in Patent Office: 446 Days
• Field of Search: 365/185.24, 365/185.03
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.

Claims

1. A nonvolatile semiconductor memory device comprising:

a plurality of data lines;

a plurality of source lines;

a plurality of memory cells each of which has a threshold voltage corresponding to data of at least two bits, and each of which is coupled to a corresponding data line of said plurality of data lines and which is coupled to a corresponding source line of said plurality of source lines;

wherein each of said plurality of memory cells is programmed with data by using a tunnel effect in a program mode, and wherein a threshold voltage of each of said plurality of memory cells is distributed in one of at least four threshold voltage distributions; and

a word driver circuit applying a read voltage to one or more selected memory cells a plurality of times in a read mode,

wherein said read voltage has at least three voltage levels,

wherein, in said read mode, each of source lines coupled to said selected memory cells is coupled so as to be applied with a predetermined potential; and

wherein a first read voltage is first applied to said selected memory cells, and then at least two other read voltages at levels higher than said first read voltage are successively applied to said selected memory cells in order to successively read data starting with data corresponding to a lowest threshold voltage distribution and ending with data corresponding to a highest threshold voltage distribution.

2. A nonvolatile semiconductor memory device according to claim 1, further comprising sense latch circuits each of which is coupled to a corresponding data line of said plurality of data lines, and which latches data read from said selected memory cells.

3. A nonvolatile semiconductor memory device according to claim 2, further comprising precharge circuits each of which is coupled to a corresponding data line of said plurality of data lines.

4. A nonvolatile semiconductor memory device according to claim 3, wherein said word driver circuit supplies a first read voltage to said selected memory cells when reading data corresponding to the lowest threshold value in a first read operation of said read mode, a second read voltage higher than said first read voltage to said selected memory cells when reading data corresponding to the second-lowest threshold value in a second read operation of said read mode, and a third read voltage higher than said second read voltage to said selected memory cells when reading data corresponding to the third-lowest threshold value in a third read operation of said read mode;

and

said precharge circuits supply a prechage potential to said plurality of data lines in said first read operation, supply said precharge potential to a data line coupled to a sense latch circuit in which latched data is stored of a predetermined state in said first read operation, in said second read operation, and supply said precharge potential to a data line coupled to a sense latch circuit in which latched data is stored of said predetermined state in said second read operation, in said third read operation.

5. A nonvolatile semiconductor memory device according to claim 4, wherein each of said source lines coupled to said memory cells coupled to said selected memory cells is applied with a ground potential in said read mode.

6. A nonvolatile semiconductor memory device according to claim 5, further comprising a plurality of word lines each of which is coupled with memory cells of said plurality of memory cells, wherein said read voltage from said word driver circuit is applied to a word line coupled with said selected memory cells.

7. A nonvolatile semiconductor memory device comprising:

a plurality of data lines;

a plurality of source lines;

a plurality of memory cells each of which has a threshold voltage corresponding to data of at least two bits, and each of which is coupled to a corresponding data line of said plurality of data lines and which is coupled to a corresponding source line of said plurality of source lines,

wherein each of said plurality of memory cells is programmed with data by using a tunnel effect in a program mode, and wherein a threshold voltage of each of said plurality of memory cells is allocated to one of at least four threshold voltage ranges; and

a word driver circuit applying a read voltage to one or more selected memory cells a plurality of times in a read mode,

wherein, in said read mode, each of source lines coupled to said selected memory cells is coupled so as to be applied with a predetermined potential, and

wherein voltage levels of said read voltage applied to said selected memory cells in order are increased so as to successively read from data corresponding to the lowest threshold voltage range to data corresponding to the highest threshold voltage range.

8. A nonvolatile semiconductor memory device according to claim 7, further comprising sense latch circuits each of which is coupled to a corresponding data line of said plurality of data lines, and which latches data of memory cells coupled to said selected memory cells.

9. A nonvolatile semiconductor memory device according to claim 8, further comprising precharge circuits each of which is coupled to a corresponding data line of said plurality of data lines.

10. A nonvolatile semiconductor memory device according to claim 9, wherein said word driver circuit supplies a first read voltage to said selected memory cells when reading data corresponding to the lowest threshold range in a first read operation of said read mode, a second read voltage higher than the first read voltage to said selected memory cells when reading data corresponding to the second-lowest threshold range in a second read operation of said read mode, and a third read voltage higher than said second read voltage to said selected memory cells when reading data corresponding to the third-lowest threshold range in a third read operation of said read mode;

and

said precharge circuits supply a precharge potential to said plurality of data lines in said first read operation, supply said precharge potential to a data line coupled to a sense latch circuit in which latched data is stored of a predetermined state in said first read operation, in said second read operation, and supply said precharge potential to a data line coupled to a sense latch circuit in which latched data is stored of said predetermined state in said second read operation, in said third read operation.

11. A nonvolatile semiconductor memory device ac(or(ling to claim 10, wherein each of said source lines coupled to said selected memory cells is applied with a ground potential in said read mode.

12. A nonvolatile semiconductor memory device according to claim 11, further comprising a plurality of word lines each of which is coupled with memory cells of said plurality of memory cells, wherein said read voltage from said word driver circuit is applied to a word line coupled with said selected memory cells.

13. A nonvolatile semiconductor memory device comprising:

a plurality of first data lines;

a plurality of source lines;

a plurality of sense latch circuits, each of which has a pair of terminals, and each of which is coupled with said plurality of first data lines to one of said pair of terminals;

a plurality of memory cells, each of which has a threshold voltage corresponding to data of at least two bits, each of which is coupled to a corresponding data line of said plurality of first data lines, and each of which is coupled to a corresponding source line of said plurality of source lines;

a plurality of first precharge circuits each of which is coupled to a corresponding first data line of said plurality of first data lines;

wherein each of said plurality of memory cells is programmed with data by using a tunnel effect in a program mode, and wherein a threshold voltage of each of said plurality of memory cells is distributed in one of at least four threshold voltage distributions; and

a word driver circuit applying a read voltage to selected memory cells a plurality of times in a read mode,

wherein said read mode includes at least first, second and third read operations,

wherein, in said read mode, each of source lines coupled to said selected memory cells is coupled so as to be applied with a predetermined potential,

wherein said selected memory cells are first applied with a read voltage of a first level between the lowest threshold voltage distribution and the second lowest threshold voltage distribution in said first read operation,

said selected memory cells are secondly supplied with a second read voltage of a second level between the second lowest threshold voltage distribution and the third lowest threshold voltage distribution in said second read operation, and

said selected memory cells are thirdly applied with a third read voltage of a third level between the third lowest threshold voltage distribution and the fourth lowest threshold voltage distribution in said third read operation, and

wherein after a first sense latch circuit of said sense latch circuits senses data of a predetermined state in said first read operation, a data line coupled to said first sense circuit is not precharged in said second read operation, and

after a second sense latch circuit of said sense latch circuits senses data of said predetermined state in said second read voltage, data lines coupled to said first and said second sense circuits are not precharged in said third read operation.

14. A nonvolatile semiconductor memory device according to claim 13, wherein each of said plurality of sense latch circuits has a function for latching sensed data.

15. A nonvolatile semiconductor memory device according to claim 14, wherein said data line coupled to said first sense latch circuit is set to a ground potential in said second read operation, and

wherein said data lines coupled to said first and said second latch sense circuits are set to said ground potential in said third read operation.

16. A nonvolatile semiconductor memory device according to claim 15, further comprising a terminal, wherein each of said program mode and said read mode is respectively set by a program command and a read command inputted from said terminal.

17. A nonvolatile semiconductor memory device according to claim 16, wherein data and address signals are inputted from said terminal.

18. A nonvolatile semiconductor memory device according to claim 17, further comprising a plurality of second data lines each of which is coupled to the other of said pair of terminals of said plurality of sense latch circuits.

19. A nonvolatile semiconductor memory device according to claim 18, further comprising a plurality of second precharge circuits each of which is coupled to a corresponding second data line of said plurality of second data lines.

20. A nonvolatile semiconductor memory device according to claim 19, wherein each of said plurality of second precharge circuits precharge said plurality of second data lines to a reference level lower than a precharge level of said plurality of first precharge circuits.

21. A nonvolatile semiconductor memory device according to claim 20, further comprising, a plurality of first data latch circuits each of which is coupled to a corresponding first data line of said plurality of first data lines, and a plurality of second data latch circuits each of which is coupled to a corresponding second data line of said plurality of second data lines.

22. A nonvolatile semiconductor memory device according to claim 21, wherein first data sensed by said sense latch circuits in said first read operation are transferred to and stored in said first data latch circuits before said second read operation,

wherein second data sensed by said sense latch circuits in said second read operation are transferred to and stored in said second data latch circuits before said third read operation,

wherein third data sensed by said sense latch circuits in said third read operation are stored in said sense latch circuits,

wherein a predetermined operation processing of said second data and said third read data is executed, and

wherein data representing the result of executing the predetermined operation processing is stored in said second data latch circuits.

23. A nonvolatile semiconductor memory device according to claim 20, further comprising a terminal, wherein each of said program mode and said read mode is respectively set by a program command and a read command inputted from said terminal, and

wherein said first data stored to said first data latch circuits and the execution result data stored in said second data latch circuits are outputted from said terminal.

24. A nonvolatile semiconductor memory device according to claim 23, further comprising a power supply circuit generating said first, said second and said third read voltage.

25. A nonvolatile semiconductor memory device according to claim 24, wherein each of said source lines coupled to said selected memory cells is applied with a ground potential in said read mode.

26. A nonvolatile semiconductor memory device according to claim 25, further comprising a plurality of word lines each of which is coupled with memory cells of said plurality of memory cells, wherein said read voltage from said word driver circuit is applied to a word line coupled with said selected memory cells.

27. A multi level nonvolatile semiconductor memory device comprising:

a plurality of data lines;

a plurality of source lines;

a plurality of memory cells each of which has a threshold voltage corresponding to data of at least two bits, and each of which is coupled to a corresponding data line of said plurality of data lines and which is coupled to a corresponding source line of said plurality of source lines,

wherein each of said plurality of memory cells is coupled to a corresponding data line of said plurality of data lines and is coupled to a corresponding source line of said plurality of source lines, and

wherein a threshold voltage of each of said plurality of memory cells is allocated in one of at least four threshold voltage ranges,

a word driver circuit applying a read voltage to one or more selected memory cells a plurality of times in a read mode;

sense circuits each of which has a pair of terminals and each of which is coupled by one of said pair of terminals to a corresponding data line of said plurality of data lines, and which senses data of one of a first state and a second state read from said selected memory cells; and

first precharge circuits each of which is coupled to a corresponding data line of said plurality of data lines and to a corresponding sense circuit of said sense circuits, and each of which precharges a corresponding data line to a prechrage potential in response to data sensed by said sense circuit, in said read mode,

wherein said read mode includes at least first, second and third read operations,

wherein, in said read mode, each of source lines coupled to said selected memory cells is coupled so as to be applied with a predetermined potential,

wherein said selected memory cells are first applied with a first read voltage of a first level between the lowest threshold voltage range and the second lowest threshold voltage range in said first read operation,

said selected memory cells are secondly applied with a second read voltage of a second level between the second lowest threshold voltage range and the third lowest threshold voltage range in said second read operation, and

said selected memory cells are thirdly applied with a third read voltage of a third level between the third lowest threshold voltage range and the fourth lowest threshold voltage range in said third read operation, and

wherein after a first sense circuit of said sense circuits senses data of a first state in said first read operation, a data line coupled to said first sense circuit is inhibited from a precharge by one of said first precharge circuits coupled to said first sense circuit in said second read operation, and

after a second sense circuit of said sense circuits senses data of said first state in said second read voltage, data lines coupled to said first and said second sense circuit are inhibited from a precharge by one of said first precharge circuits coupled to said first and said second sense circuits in said third read operation.

28. A multi level nonvolatile semiconductor memory device according to claim 27, wherein each of said sense circuits has a function for latching sensed data.

29. A multi level nonvolatile semiconductor memory device according to claim 28, wherein said data line coupled to said first sense circuit is set to a ground potential in said second read operation, and

wherein said data lines coupled to said first and said second sense circuits are set to said ground potential in said third read operation.

30. A multi level nonvolatile semiconductor memory device according to claim 29, further comprising a terminal, wherein said program mode and said read mode are respectively set by a program command and a read command inputted from said terminal.

31. A multi level nonvolatile semiconductor memory device according to claim 30, wherein data and address signals are inputted from said terminal.

32. A multi level nonvolatile semiconductor memory device according to claim 31, further comprising a plurality of second data lines each of which is coupled to the other of said pair of terminals of said sense circuits.

33. A multi level nonvolatile semiconductor memory device according to claim 32, further comprising a plurality of second precharge circuits each of which is coupled to a corresponding second data line of said plurality of second data lines.

34. A multi level nonvolatile semiconductor memory device according to claim 33, wherein each of said plurality of second precharge circuits precharge said plurality of second data lines to a reference level lower than a precharge level of said plurality of first precharge circuits.

35. A multi level nonvolatile semiconductor memory device according to claim 34, further comprising, a plurality of first data latch circuits each of which is coupled to a corresponding first data line of said plurality of first data lines, and a plurality of second data latch circuits each of which is coupled to a corresponding second data line of said plurality of second data lines.

36. A multi level nonvolatile semiconductor memory device according to claim 35, wherein first data sensed by said sense circuits in said first read operation are transferred to and stored in said first data latch circuits before said second read operation,

wherein second data sensed by said sense circuits in said second read operation are transferred to and stored in said second data latch circuits before said third read operation,

wherein third data sensed by said sense circuits in said third read operation are stored in said sense circuits,

wherein a predetermined operation processing of said second data and said third read data is executed, and

wherein data representing the result of executing the predetermined operation processing is stored in said second data latch circuits.

37. A multi level nonvolatile semiconductor memory device according to claim 36, wherein said first data stored in said first data latch circuits and the execution result data stored in said second data latch circuits are outputted from said terminal.

38. A multi level nonvolatile semiconductor memory device according to claim 37, further comprising a power supply circuit generating said first, said second and said third read voltages in said read mode.

39. A multi level nonvolatile semiconductor memory device according to claim 38, wherein each of said source lines coupled to said selected memory cells is applied with a ground potential in said read mode.

40. A multi level nonvolatile semiconductor memory device according to claim 39, further comprising a plurality of word lines each of which is coupled with memory cells of said plurality of memory cells, wherein said read voltage from said word driver circuit is applied to a word line coupled with said selected memory cells.