Non-volatile flip-flop circuit

• US 6,222,765 B1
• Filed: 02/18/2000
• Issued: 04/24/2001
• Est. Priority Date: 02/18/2000
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Nojima, Isao
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/507,570
• Time in Patent Office: 431 Days
• Field of Search: 365/185.01, 365/185.07, 365/185.08, 365/185.1
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

A combination non-volatile latch circuit has a volatile latch circuit having a bit signal and an inverse bit signal. A first and a second non-volatile cell of the split gate floating gate type having a first terminal, a second terminal and a control gate is supplied. A first switch supplies the bit signal to the first terminal of the first cell and the inverse bit signal to the first terminal of the second cell. A second switch supplies the bit signal to the first terminal of the second cell and the inverse bit signal to the first terminal of the first cell. A first voltage can be supplied to the second terminal of the first and second cells and a second voltage supplies a voltage to the control gate of the first and second cells. In this manner, the latch can be operated independently of the non-volatile memory cells, the status of the latch can be restored by the status of the non-volatile memory cells, and the contents of the latch can be stored in the non-volatile memory cells.

Claims

1. A non-volatile flip-flop circuit comprising:

a volatile flip-flop having a bit signal and an inverse bit signal;

a first and a second non-volatile cell, each having a first terminal and a second terminal with a channel therebetween, a floating gate over a first portion of said channel, and a portion of said second terminal and a control gate over a second portion of said channel;

a first switch for supplying said bit signal to said first terminal of said first cell and said inverse bit signal to said first terminal of said second cell;

a second switch for supplying said bit signal to said first terminal of said second cell and said inverse bit signal to said first terminal of said first cell;

first means for supplying a first voltage to said second terminal of said first and second cells; and

second means for supplying a second voltage to said control gate of said first and second cells.

2. The circuit of claim 1 wherein said first switch comprises:

a first MOS transistor having a first terminal, a second terminal with a channel therebetween, and a gate for controlling the flow of current therebetween;

a second first MOS transistor having a first terminal, a second terminal with a channel therebetween, and a gate for controlling the flow of current therebetween;

said first terminal of said first MOS transistor for receiving said bit signal, said second terminal of said first MOS transistor connected to said first terminal of said first cell;

said first terminal of said second MOS transistor for receiving said inverse bit signal, said second terminal of said second MOS transistor connected to said first terminal of said second cell; and

said gate of said first and second MOS transistors connected together for receiving a first switching signal.

3. The circuit of claim 2 wherein said first switching signal activates said first switch for storing status of said flip-flop in said first and second cells.

4. The circuit of claim 2 wherein said second switch comprises:

a third MOS transistor having a first terminal, a second terminal with a channel therebetween, and a gate for controlling the flow of current therebetween;

a four MOS transistor having a first terminal, a second term with a channel therebetween, and a gate for controlling the flow of current therebetween;

said first terminal of said third MOS transistor for receiving said bit signal, said second terminal of said third MOS transistor connected to said first terminal of said second cell;

said first terminal of said fourth MOS transistor for receiving said inverse bit signal, said second terminal of said fourth MOS transistor connected to said first terminal of said first cell; and

said gate of said third and fourth MOS transistor connected together for receiving a second switching signal.

5. The circuit of claim 4 wherein said second switching signal activates said second switch for storing status of said first and second cells in said flip-flop.

6. The circuit of claim 1 wherein each of said first and second cells further comprising:

a first insulating layer between said floating gate and said channel, permitting hot election injection of electrons from said first terminal as they traverse to said second terminal.

7. The circuit of claim 6 wherein each of said first and second cells further comprising:

a second insulating layer between said floating gate and said control gate permitting Fowler-Nordheim tunneling of electrons from said floating gate to said control gate.