High-speed SRAM having a stable cell ratio

• US 6,222,780 B1
• Filed: 03/09/2000
• Issued: 04/24/2001
• Est. Priority Date: 03/10/1999
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Takahashi, Hiroyuki
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US09/521,965
• Time in Patent Office: 411 Days
• Field of Search: 365/154, 365/189.09, 365/214, 365/226, 365/230.06
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A SRAM includes four-transistor memory cells each operating in a data hold mode using an off-leak current supplied from a digit line through a transfer transistor in an off-state. The cell ratio of the memory cell is determined by a reference voltage which has un-uniformity corresponding to un-uniformity of the cell ratio, thereby offering a stable data hold operation and a higher-speed equalization of digit lines.

Claims

1. A SRAM comprising a plurality of memory cells arranged in a matrix and each including a pair of transfer transistors and a pair of driver transistors operatively connected for storing a cell data on a pair of internal nodes, a word line disposed for each row of said memory cells for driving gates of said transfer transistors of said memory cells in the each row, a pair of digit lines disposed for each column of said memory cells for transferring data through said transfer transistors of said memory cells in the each column, a word line driver disposed for each word line for activating the each word line, one of said driver transistors passing an off-leak current supplied from a corresponding one of said digit lines through a corresponding one of said transfer transistors in an off-state thereof to store the cell data, a precharge section for connecting said digit lines to a first source line for precharging, a write amplifier and a sense amplifier disposed for each column of said memory cells for storing/reading data through said digit lines into/from said memory cells in the each column, and a reference voltage generator for generating a reference voltage which determines a cell ratio of each memory cell, the reference voltage having un-uniformity corresponding to un-uniformity of a potential of one of said internal nodes assuming a high level or low level.

2. The SRAM as defined in claim 1, wherein said transfer transistors are of pMOS type and said driver transistors are of nMOS type.

3. The SRAM as defined in claim 2, wherein said reference voltage generator includes a pMOS transistor and an nMOS transistor connected in series between said first source line and a ground line, and a voltage follower having an input connected to a node connecting said pMOS transistor and said nMOS transistor and an output for outputting the reference voltage.

4. The SRAM as defined in claim 2, wherein said reference voltage generator and a part of said memory cell form a current mirror.

5. The SRAM as defined in claim 4, wherein said write amplifier delivers a write signal having a potential higher than a potential of said first source line.

6. The SRAM as defined in claim 1, wherein said reference voltage determines a higher voltage level for a driving signal supplied from said word line driver.

7. The SRAM as defined in claim 1, wherein said reference voltage determines a lower voltage level for a driving signal supplied from said word line driver.

8. The SRAM as defined in claim 1, wherein said reference voltage determines a potential of an n-well of said transfer transistors.

9. The SRAM as defined in claim 1, wherein said reference voltage generator includes a pMOS transistor and an nMOS transistor connected in series between said first source line and the ground line, and an operational amplifier having a first input connected to a node connecting said pMOS transistor and said nMOS transistor, a second input connected to a constant potential line and an output connected to an n-well of said pMOS transistor and delivering the reference voltage.