High-speed SRAM having a stable cell ratio
First Claim
1. A SRAM comprising a plurality of memory cells arranged in a matrix and each including a pair of transfer transistors and a pair of driver transistors operatively connected for storing a cell data on a pair of internal nodes, a word line disposed for each row of said memory cells for driving gates of said transfer transistors of said memory cells in the each row, a pair of digit lines disposed for each column of said memory cells for transferring data through said transfer transistors of said memory cells in the each column, a word line driver disposed for each word line for activating the each word line, one of said driver transistors passing an off-leak current supplied from a corresponding one of said digit lines through a corresponding one of said transfer transistors in an off-state thereof to store the cell data, a precharge section for connecting said digit lines to a first source line for precharging, a write amplifier and a sense amplifier disposed for each column of said memory cells for storing/reading data through said digit lines into/from said memory cells in the each column, and a reference voltage generator for generating a reference voltage which determines a cell ratio of each memory cell, the reference voltage having un-uniformity corresponding to un-uniformity of a potential of one of said internal nodes assuming a high level or low level.
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Accused Products
Abstract
A SRAM includes four-transistor memory cells each operating in a data hold mode using an off-leak current supplied from a digit line through a transfer transistor in an off-state. The cell ratio of the memory cell is determined by a reference voltage which has un-uniformity corresponding to un-uniformity of the cell ratio, thereby offering a stable data hold operation and a higher-speed equalization of digit lines.
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Citations
9 Claims
- 1. A SRAM comprising a plurality of memory cells arranged in a matrix and each including a pair of transfer transistors and a pair of driver transistors operatively connected for storing a cell data on a pair of internal nodes, a word line disposed for each row of said memory cells for driving gates of said transfer transistors of said memory cells in the each row, a pair of digit lines disposed for each column of said memory cells for transferring data through said transfer transistors of said memory cells in the each column, a word line driver disposed for each word line for activating the each word line, one of said driver transistors passing an off-leak current supplied from a corresponding one of said digit lines through a corresponding one of said transfer transistors in an off-state thereof to store the cell data, a precharge section for connecting said digit lines to a first source line for precharging, a write amplifier and a sense amplifier disposed for each column of said memory cells for storing/reading data through said digit lines into/from said memory cells in the each column, and a reference voltage generator for generating a reference voltage which determines a cell ratio of each memory cell, the reference voltage having un-uniformity corresponding to un-uniformity of a potential of one of said internal nodes assuming a high level or low level.
Specification