Vertical gate transistors in pass transistor logic decode circuits
First Claim
1. An address decoder for a memory device, comprising:
- a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array; and
a number logic cells that are disposed at the intersections of output lines and address lines, wherein each of the logic cells includes;
a source region in a horizontal substrate;
a drain region in the horizontal substrate;
a depletion mode channel region separating the source and the drain regions;
a number of vertical gates located above different portions of the depletion mode channel region;
wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and
wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
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Abstract
Systems and methods are provided for vertical gate transistors in static pass transistor decode circuits. The vertical gate transistors have multiple vertical gates which are edge defined such that only a single transistor is required for multiple logic inputs. Thus a minimal surface area is required for each logic input. The novel decode circuits of the present invention include an address decoder for a memory device. The decode circuit includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number logic cells that disposed at the intersections of output lines and address lines. According to the teachings of the present invention each logic cell includes a source region and a drain region in a horizontal substrate. A depletion mode channel region separates the source and the drain regions. A number of vertical gates are located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. At least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. According to the present invention, there is no source nor drain region associated with each input and the gates have sub-lithographic horizontal dimensions by virtue of being edge defined vertical gates.
91 Citations
73 Claims
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1. An address decoder for a memory device, comprising:
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a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array; and
a number logic cells that are disposed at the intersections of output lines and address lines, wherein each of the logic cells includes;
a source region in a horizontal substrate;
a drain region in the horizontal substrate;
a depletion mode channel region separating the source and the drain regions;
a number of vertical gates located above different portions of the depletion mode channel region;
wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and
wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A decode circuit for a semiconductor memory, comprising:
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a number of logic cells having a source region, a drain region, and a horizontal depletion mode channel therebetween, wherein each logic cell includes;
a first vertical gate separated from a first portion of the depletion mode channel region by a first oxide thickness; and
a second vertical gate separated from a second portion of the depletion mode channel region by a second oxide thickness, wherein the first vertical gate is formed opposing the second vertical gate;
a number of address lines coupled to the gates of the number of logic cells; and
a number of output lines coupled to the drain region of the number of logic cells. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A decode circuit for a semiconductor memory, comprising:
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a number of logic cells having a source region, a drain region, and a horizontal depletion mode channel therebetween, wherein each logic cell includes;
a first vertical gate located above a first portion of the depletion mode channel region and separated from the depletion mode channel region by a first oxide thickness;
a second vertical gate located above a second portion of the depletion mode channel region and separated from the depletion mode channel region by a second oxide thickness, and a third vertical gate located above a third portion of the depletion mode channel region and separated from the depletion mode channel region by the second oxide thickness;
a number of address lines coupled to the gates of the number of logic cells; and
a number of output lines coupled to the drain region of the number of logic cells. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. A memory address decoder, comprising:
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a number of static pass transistors, wherein each of the static pass transistors includes;
a horizontal substrate, wherein the substrate includes a source region, a drain region, and a depletion mode channel region separating the source and the drain region;
a first vertical gate separated from a first portion of the depletion mode channel region by a first oxide thickness; and
a second vertical gate separated from a second portion of the depletion mode channel region by a second oxide thickness, wherein the second vertical gate is parallel to the first vertical gate; and
a number of address lines coupled to the gates of the number of static pass transistors; and
a number of output lines coupled to the drain region of the number of static pass transistors. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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31. A memory device, comprising:
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an array of memory cells;
a decode circuit coupled to the array of memory cells, wherein the decode circuit includes a plurality of logic cells, and wherein each logic cell includes;
a horizontal substrate, wherein the substrate includes a source region, a drain region, and a depletion mode channel region separating the source and the drain region;
a first vertical gate located above a first portion of the depletion mode channel region and separated from the depletion mode channel region by a first oxide thickness;
a second vertical gate located above a second portion of the depletion mode channel region and separated from the depletion mode channel region by a second oxide thickness, and a third vertical gate located above a third portion of the depletion mode channel region and separated from the depletion mode channel region by the second oxide thickness; and
at least one sense amplifier, wherein the at least one sense amplifier couples to the plurality of logic cells. - View Dependent Claims (32, 33, 34, 35, 36)
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37. An electronic system, comprising:
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a processor; and
a memory device coupled to the processor, wherein the memory device includes a decode circuit, the decode circuit having a plurality of logic cells, and wherein each logic cell includes;
a horizontal substrate, wherein the substrate includes a source region, a drain region, and a depletion mode channel region separating the source and the drain region;
a number of vertical gates located above different portions of the depletion mode channel region;
wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first oxide thickness; and
wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second oxide thickness. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44)
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45. A method for forming a decode circuit, comprising:
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forming a number of address lines;
forming a number of output lines;
forming a number of logic cells having gates coupled to the address lines and drain regions coupled to the output lines, wherein forming the number of logic cells includes;
forming a source region and a drain region in a horizontal substrate;
forming a depletion mode channel in the horizontal substrate between the source and the drain regions;
forming a number of vertical gates above different portions of the depletion mode channel;
wherein forming a number of vertical gates includes forming at least one of the vertical gates separated from the depletion mode channel by a first oxide thickness (t1); and
wherein forming a number of vertical gates includes forming at least one of the vertical gates separated from the depletion mode channel region by a second oxide thickness (t2). - View Dependent Claims (46, 47, 48, 49, 50, 51, 52)
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53. A method for forming a memory address decoder, comprising:
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forming a number of logic cells, wherein forming a number of logic cells includes;
forming a source region and a drain region in a horizontal substrate;
forming a depletion mode channel between the source and the drain regions;
forming a first vertical gate located above a first portion of the depletion mode channel and separated from the depletion mode channel by a first oxide thickness;
forming a second vertical gate located above a second portion of the depletion mode channel and separated from the depletion mode channel by a second oxide thickness; and
forming a third vertical gate located above a third portion of the depletion mode channel and separated from the depletion mode channel by the second oxide thickness. - View Dependent Claims (54, 55, 56, 57, 58, 59)
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60. A method for operating a decode circuit, comprising:
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applying a number of address signals to a number of logic cells, wherein applying a number of address signals to the number of logic cells includes applying a potential to a number of vertical gates located above different portions of a horizontal depletion mode channel, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, and wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness; and
sensing a conduction level through the depletion mode channel for decoding a row line. - View Dependent Claims (61, 62, 63, 64)
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65. A method for operating a memory decode circuit, comprising:
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addressing a number of logic cells, wherein addressing a number of logic cells includes using a number of vertical gates located above a horizontal depletion mode channel between a single source region and a single drain region to provide an applied potential above the depletion mode channel, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, and wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness vertical;
using at least one of the number of vertical gates as a passing line such that a potential on the passing line does not effect conduction in the depletion mode channel; and
using at least two of the number of vertical gates as a number of active inputs such that the active inputs control conduction in the depletion mode channel for decoding a row line. - View Dependent Claims (66, 67, 68, 69, 70, 71, 72, 73)
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Specification