Apparatus for low power radio communications

• US 6,223,061 B1
• Filed: 07/25/1997
• Issued: 04/24/2001
• Est. Priority Date: 07/25/1997
• Status: Expired due to Term

• Current Assignee: Cleveland Medical Devices Inc.
• Original Assignee: Cleveland Medical Devices Inc.
• Inventors: Schmidt, Robert N., Dacus, Farron L., Hendrix, Steven P.
• Primary Examiner(s): Eisenzopf, Reinhard
• Assistant Examiner(s): Aoki, Makoto
• Application Number:
  US08/900,329
• Time in Patent Office: 1,369 Days
• Field of Search: 455/119, 455/38.3, 455/180.3, 455/180.4, 455/260, 455/522, 455/574, 375/211, 375/223, 375/272, 375/303, 375/334, 331/14, 331/17, 331/23, 331/41, 332/10, 332/127
• US Class Current: 455/574
• CPC Class Codes: H03C 3/095 applying frequency modulation to the loop in front of the voltage controlled oscillator
• CPC Class Codes: H03C 3/0958 applying frequency modulation by varying the characteristics of the voltage controlled oscillator
• CPC Class Codes: H03J 7/04 where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

An apparatus for low power radio communication comprising a transmitter having a frequency synthesizer and transmit antenna such that the frequency synthesizer comprises a phase locked loop circuit with a voltage controlled oscillator having a variable frequency output and with a loop filter/sample and hold circuit that allows opening of the synthesizer control loop and with special means of limiting the resulting frequency drift in the open loop state. The transmitter produces an output signal and the loop filter/sample and hold circuit holds the voltage controlled oscillator substantially on frequency such that the output signal remains stable, with a minimum of frequency drift, over a period of time when the phase lock loop synthesizer is set to an open loop state to allow frequency modulation unimpeded by the normal frequency correcting action of the synthesizer and for the frequency synthesizer to be partially powered down to reduce power consumption. The frequency modulation is linearized over a band of interest and undesired frequency shift at the initiation of modulation is suppressed. Receiver having automatic frequency control is included to extend the open loop transmit time of the transmitter, where the automatic frequency control system automatically tunes the receiver to correct for frequency error and for the frequency drift resulting from opening the phase locked loop of the frequency synthesizer, allowing communications to continue in the presence of such drift and of other frequency error.

Claims

1. A transmitting means for efficient low power radio communication, the transmitting means operates with a certain frequency modulated frequency deviation over a certain carrier frequency range, comprising:

a) DC cancellation mid-point modulation means utilizing a DC compensating signal having a non-modulation state and a modulation state such that said DC compensating signal changes from said non-modulation state to said modulation state upon commencement of modulation and remains in said modulation state so long as modulation continues, and a data signal having a DC voltage content which swings between end points around a nominal mid-point, and having a state prior to modulation commencing opposite to the state of said DC compensating signal;

b) resistive summing circuit which sums said DC compensating signal and said data signal such that the component in the sum due to said DC compensating signal cancels the change in the DC content of the component in the sum due to initiation of modulation by said data signal resulting in a DC cancellation mid-point modulation output whereby the commencement of data modulation begins from said nominal mid-point between said end points of said DC voltage content swing of said data signal and such that there is no change in the average DC level of said DC cancellation mid-point modulation output in said non-modulation and modulation states; and

c) frequency synthesizing means incorporating said DC cancellation mid-point modulation means and further comprising a phase locked loop circuit, having open and close loop conditions, with a voltage controlled oscillator having an VCO output of variable frequency, and a loop filter/sample and hold circuit, said loop filter/sample and hold circuit switches said phase lock loop circuit between said open loop and close loop conditions, such that said output signal remains stable and substantially on frequency when said phase locked loop circuit is in said open loop condition, with a minimum of frequency drift over a period of time and whereby said DC cancellation mid-point modulation means causes the frequency deviation of the frequency modulation to vary approximately equally around the desired carrier frequency over which said transmitting means may operate.