Multiple use chip socket for integrated circuits and the like

• US 6,223,147 B1
• Filed: 03/31/1993
• Issued: 04/24/2001
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bowers, Richard
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US08/040,528
• Time in Patent Office: 2,946 Days
• Field of Search: 364/489, 364/490, 364/200, 364/578, 371/25, 365/189, 365/196, 365/104, 395/375, 395/575, 395/500, 395/800, 703/25, 703/27, 703/28, 703/21
• US Class Current: 703/25
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00

Abstract

A multiple use chip socket supporting more than one type of permanent storage chip in a single chip socket is disclosed. The multiple use chip socket provides a plurality of address bit lines which are used to specify an address of a particular location within a memory device installed in the socket. In general, the number of address bit lines directly coupled to the socket correspond to the number of address bit lines required for the smallest memory device to be installed in the socket. Additional address bit lines are coupled to control logic of the present invention. The control logic selectively applies addressing signals to the chip socket depending on the type of memory device inserted in the socket. As part of the initialization process, the processing logic of the present invention first determines if an access to a device installed in the chip socket is required by a circuit board as part of its initialization or boot process. If such an access is required, the processing logic then determines if a device is installed in the chip socket. If a device is installed in the chip socket, the processing logic then determines if the device is a flash device or an EPROM device or other type of device. In this manner, the accessing signals appropriate for the particular type of device can be configured.

Claims

1. A multiple use chip socket comprising:

a chip socket for receiving either a first chip type or a second chip type, said first chip type having a first set of signals, said second chip type having a second set of signals different from said first set of signals; and

control logic coupled to said chip socket for determining whether a chip of said first chip type or said second chip type is installed in said chip socket by reading a predetermined memory location of a chip installed in said chip socket and for providing signals to said chip socket compatible with either said first set of signals or said second set of signals to configure said chip socket to support operation of either said first chip type or said second chip type installed in said chip socket.

2. The multiple use chip socket as claimed in claim 1 wherein said first chip type is an EPROM chip type and said second chip type is a flash memory chip type.

3. The multiple use chip socket as claimed in claim 1 wherein said control logic further includes logic for selectively providing to a particular pin of said socket either a Vcc voltage if a chip of said first chip type is installed in said chip socket or an address signal if a chip of said second chip type is installed in said chip socket.

4. The multiple use chip socket as claimed in claim 1 wherein said control logic further includes logic for selectively holding a fixed logic level on a particular pin of said socket if a chip of said first chip type is installed in said chip socket or providing an address signal to said particular pin of said socket if a chip of said second chip type is installed in said chip socket.

5. The multiple use chip socket as claimed in claim 1 wherein said control logic further includes logic for determining whether or not a device is installed in said chip socket.

6. The multiple use chip socket as claimed in claim 1, wherein said control logic further comprises logic for determining if said chip installed in said multiple use chip socket is required to be accessed as a boot device.

7. The multiple use chip socket as claimed in claim 1, wherein said first chip type and said second chip type are memory chips, and wherein operation of said first chip type and said second chip type includes a memory read operation or a memory write operation.

8. A computer system comprising:

an address bus and a control bus;

a processor coupled to said address bus and said control bus for transferring a memory access request to a memory chip; and

a multiple use chip socket coupled to said address bus and said control bus, said multiple use chip socket further including;

a.) a chip socket for receiving either a first chip type or a second chip type, said first chip type having a first set of signals, said second chip type having a second set of signals different from said first set of signals; and

b.) control logic coupled to said chip socket for determining whether a chip of said first chip type or said second chip type is installed in said chip socket and for providing signals to said chip socket compatible with either said first set of signals or said second set of signals to configure said chip socket to support operation of either said first chip type or said second chip type installed in said chip socket, said control logic including logic for reading a predetermined memory location of a chip installed in said chip socket to determine whether a chip of said first chip type or said second chip type is installed in said chip socket.

9. The computer system as claimed in claim 8 wherein said first chip type is an EPROM chip type and said second chip type is a flash memory chip type.

10. The computer system as claimed in claim 8 wherein said control logic further includes logic for selectively providing to a particular pin of said socket either a Vcc voltage if a chip of said first chip type is installed in said chip socket or an address signal if a chip of said second chip type is installed in said chip socket.

11. The computer system as claimed in claim 8 wherein said control logic further includes logic for selectively holding a fixed logic level on a particular pin of said socket if a chip of said first chip type is installed in said chip socket or providing an address signal to said particular pin of said socket if a chip of said second chip type is installed in said chip socket.

12. The computer system as claimed in claim 8 wherein said control logic further includes logic for determining whether or not a device is installed in said chip socket.

13. The multiple use chip socket as claimed in claim 8, wherein said control logic further comprises logic for determining if said chip installed in said multiple use chip socket is required to be accessed as a boot device.

14. A method for accessing a chip installed in a multiple use chip socket, said method comprising the steps of:

determining if said chip installed in said multiple use chip socket is required to be accessed as a boot device;

determining if a chip is installed in said multiple use chip socket;

determining if said chip installed in said multiple use chip socket is a chip of either a first chip type or a second chip type by reading a predetermined location of said chip installed in said chip socket, said first chip type having a first set of signals, said second chip type having a second set of signals different from said first set of signals; and

configuring accessing signals appropriate for either said first chip type or said second chip type depending on which type of chip is determined in said step of determining if said chip installed in said multiple use chip socket is a chip of either a first chip type or a second chip type.

15. The method as claimed in claim 14 wherein said first chip type is an EPROM chip type and said second chip type is a flash memory chip type.

16. The method as claimed in claim 14 further including the steps of:

providing a V_cc voltage to a particular pin of said socket if a chip of said first chip type is installed in said socket; and

providing an address signal to said particular pin of said socket if a chip of said second chip type is installed in said socket.

17. The method as claimed in claim 14 further including the steps of:

holding a fixed logic level on a particular pin of said socket if a chip of said first chip type is installed in said socket; and

providing an address signal to said particular pin of said socket if a chip of said second chip type is installed in said socket.

18. A multiple use chip socket comprising:

a chip socket for receiving an EPROM chip or a flash memory chip, said EPROM chip having a first set of signals, said flash memory chip having a second set of signals different from said first set of signals; and

control logic coupled to said chip socket for determining whether said EPROM chip or said flash memory chip is installed in said chip socket by reading a predetermined location of said EPROM chip or said flash chip installed in said chip socket and for providing signals to said chip socket compatible with either said EPROM chip or said flash memory chip such that memory read and memory write operations can be performed upon whichever of said EPROM chip or said flash memory chip is installed in said chip socket.