Method of peer-to-peer mastering over a computer bus

• US 6,223,238 B1
• Filed: 03/31/1998
• Issued: 04/24/2001
• Est. Priority Date: 03/31/1998
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micro Electronics Incorporated
• Inventors: Meyer, James W., Laberge, Paul A.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/053,378
• Time in Patent Office: 1,120 Days
• Field of Search: 710/105, 710/126, 710/128, 710/129, 710/107, 710/110, 710/112
• US Class Current: 710/312
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A method of communication between requester and target devices in a computer system having a multiple bus architecture. The method supports deferred transactions of cache line read requests over a host bus, e.g., the Pentium II or Pentium Pro (P6) bus. The method employs a host bridge to issue deferred transactions over the P6 bus without interrupting or involving the main processor. The method comprises the act of establishing a handshake with a host master and issuing a request over the host bus. The method further comprises the act of acknowledging the request and transmitting a deferred response to the requester.

Claims

1. In a computer system having a main processor connected to a host bus, a method of communication between at least one requester, connected to a first bus, and at least one target, connected to a second bus, the method comprising:

instructing a first device to receive a request from the requester via the first bus;

sending the request by the first device to a second device via the host bus;

asserting a defer enable signal by the first device via the host bus; and

deferring response by the target when the target is unavailable to respond.

2. The method as defined in claim 1, wherein the act of sending the request by the first device via the host bus includes the act of issuing a cache line read request via the host bus.

3. The method as defined in claim 1, wherein the act of instructing the first device includes the act of issuing a request by an IDE Controller to a host master via an internal control bus.

4. The method as defined in claim 1, wherein the act of instructing the first device includes the act of establishing a handshake between an IDE Controller and a host master.

5. The method as defined in claim 1, wherein the act of sending the request by the first device via the host bus includes the act of issuing a cache line read request by the first device via a P6 bus.

6. The method as defined in claim 1, wherein the method further comprises the act of issuing the request by the requester to an IDE Controller.

7. The method as defined in claim 1, wherein the method further comprises the act of accepting the request and a defer enable signal by the second device.

8. The method as defined in claim 1, wherein the method further comprises the act of issuing a request having a defer enable signal by the second device via the second bus.

9. The method as defined in claim 1, wherein the communication between the requester and the target involves at least one device other than the main processor.

10. In a computer system having at least one main processor connected to a host bus, a method of communication between at least one requester connected to a first bus and at least one target connected to a second bus, the method comprising:

issuing a request by the requester via the first bus to a first device;

forwarding the request with a defer enable signal by the first device to a second device via the host bus;

receiving the request by the second device from the first device via the host bus;

sending the request by the second device to the target via the second bus_{; and}

deferring response to the requester when the target is unavailable to respond.

11. The method as defined in claim 10, wherein the act of issuing the request by the requester includes the act of issuing the request by an IDE controller to the first device.

12. The method as defined in claim 10, wherein the act of forwarding the request with a defer enable signal by the first device includes the act of forwarding a cache line read request via the host bus.

13. The method as defined in claim 10, wherein the act of deferring the response to the requester includes the act of transmitting the deferred response from a PCI device.