Dual purpose apparatus, method and system for accelerated graphics port or system area network interface
First Claim
1. A computer system having a core logic chipset having an AGP bus, said computer system comprising:
- a central processing unit connected to a host bus;
said core logic chipset connected to said host bus;
system memory connected to said core logic chip set by a memory bus;
said core logic chipset configured as a first interface bridge between said host bus and said memory bus, and a second interface bridge between said host bus and a peripheral component interconnect bus connected to said core logic chipset;
said core logic chipset configurable as a third interface bridge between said host bus and said AGP bus;
said core logic chipset capable of accommodating an AGP device connected to said AGP bus when a configuration signal is set to a first logic level; and
said core logic chipset capable of accommodating a PCI device connected to said AGP bus when said configuration signal is set to a second logic level.
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Accused Products
Abstract
A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, or as a bridge between a system area network interface and the host bus and the system memory bus. The function of the multiple use chipset is determined at the time of manufacture of the computer system, or in the field whether an AGP bus bridge or a system area network interface is to be implemented. Selection of the type of bus bridge (AGP or system area network interface) in the multiple use core logic chipset may be implemented by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP device or a system area network interface connected to the core logic chipset.
53 Citations
10 Claims
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1. A computer system having a core logic chipset having an AGP bus, said computer system comprising:
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a central processing unit connected to a host bus;
said core logic chipset connected to said host bus;
system memory connected to said core logic chip set by a memory bus;
said core logic chipset configured as a first interface bridge between said host bus and said memory bus, and a second interface bridge between said host bus and a peripheral component interconnect bus connected to said core logic chipset;
said core logic chipset configurable as a third interface bridge between said host bus and said AGP bus;
said core logic chipset capable of accommodating an AGP device connected to said AGP bus when a configuration signal is set to a first logic level; and
said core logic chipset capable of accommodating a PCI device connected to said AGP bus when said configuration signal is set to a second logic level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification
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- Resources
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Current AssigneeHewlett-Packard Development Company, L.P. (HP Inc.)
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Original AssigneeCompaq Computer Corporation (HP Inc.)
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InventorsOlarig, Sompong Paul
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Primary Examiner(s)Sheikh, Ayaz
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Assistant Examiner(s)Jean, Frantz B.
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Application NumberUS09/133,788Time in Patent Office986 DaysField of Search710/129, 710/121, 710/126, 710/100, 710/101, 710/8, 712/16, 712/20, 712/14, 712/11, 712/15, 712/29, 711/202, 711/118, 711/206, 711/207, 711/147, 380/24, 380/4, 345/501, 345/514, 345/521, 345/526, 345/519, 345/520, 345/503US Class Current710/312CPC Class CodesG06F 13/387 for adaptation of different...
