Method for efficient translation of memory addresses in computer systems

• US 6,223,270 B1
• Filed: 04/19/1999
• Issued: 04/24/2001
• Est. Priority Date: 04/19/1999
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Salo, Eric, Pinkerton, James T., Chesson, Gregory L.
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US09/294,830
• Time in Patent Office: 736 Days
• Field of Search: 711/202, 711/203
• US Class Current: 711/202
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence

Abstract

A method and system for efficient translation of memory addresses in computer systems. The present invention enables address translations between different address spaces to be performed without using the table lookup step typically required in the prior art. Thus, the present invention provides significant improvements in both time and space efficiency over prior art implementations of address translation. In modern computer systems where direct memory access (DMA) operations are used extensively, especially in the emerging field of operating system (OS) bypass technology, the performance improvements afforded by the present invention are particularly critical to the realization of an efficient and high performance system. A method and system for efficiently translating memory addresses in computer systems and the address representation used are described herein.

Claims

1. A computer implemented method for performing memory address translations in a computer system, said method comprising the steps of:

a) reserving a target memory region (TMR) in a target address space, said TMR having a target base address;

b) reserving a source memory region (SMR) in a source address space, said SMR having a source base address;

c) generating a descriptor including information for resolving said target base address of said TMR; and

d) representing said TMR with said SMR in said source address space, said source base address being selected based on said descriptor such that said target base address can be computed from said source base address without using a lookup table.

2. The computer implemented method as recited in claim 1 wherein said descriptor includes a virtual address representation of said target base address.

3. The computer implemented method as recited in claim 1 wherein said source base address encodes a virtual address representation of said target base address.

4. The computer implemented method as recited in claim 1 wherein said TMR includes a target address having an offset from said target base address, said SMR includes a source address representing said target address, and said source address encodes said offset of said target address such that said target address can be computed from said source address without using a lookup table.

5. The computer implemented method as recited in claim 4 further comprising the steps of:

e) receiving a request to access said target address while operating in a context of said source address space; and

f) servicing said request to access said target address without using a lookup table.

6. The computer implemented method as recited in claim 5 wherein said step h) comprises the steps of:

f1) identifying said target address as residing outside of said source address space; and

f2) resolving said target address of said target address space using said source address of said source address space.

7. The computer implemented method as recited in claim 1 wherein said source memory region does not intersect other virtual memory regions of said source address space.

8. The computer implemented method as recited in claim 1 wherein said source address space is a 64-bit address space.

9. The computer implemented method as recited in claim 1 wherein no program code and no program data resides in memory locations of said source address space beyond said source base address.

10. The computer implemented method as recited in claim 1 wherein said target memory region comprises a plurality of target memory regions and said source memory region comprises a plurality of source memory regions, such that each of said plurality of target memory regions is represented by a unique one of said plurality of source memory regions.

11. The computer implemented method as recited in claim 1 wherein said source address space and said target address space reside in different host computers.

12. A computer system comprising:

a processor;

an address/data bus coupled to said processor;

a computer readable memory coupled to communicate with said processor, said processor for performing a method for performing memory address translations in said computer system, said method comprising the steps of;

a) reserving a target memory region (TMR) in a target address space, said TMR having a target base address;

b) reserving a source memory region (SMR) in a source address space, said SMR having a source base address;

c) generating a descriptor including information for resolving said target base address of said TMR; and

d) representing said TMR with said SMR in said source address space, said source base address being selected based on said descriptor such that said target base address can be computed from said source base address without using a lookup table.

13. The computer system as recited in claim 12 wherein said descriptor includes a virtual address representation of said target base address.

14. The computer system as recited in claim 12 wherein said source base address encodes a virtual address representation of said target base address.

15. The computer system as recited in claim 12 wherein said TMR includes a target address having an offset from said target base address, said SMR includes a source address representing said target address, and said source address encodes said offset of said target address such that said target address can be computed from said source address without using a lookup table.

16. The computer system as recited in claim 15 further comprising the steps of:

e) receiving a request to access said target address while operating in a context of said source address space; and

f) servicing said request to access said target address without using a lookup table.

17. The computer system as recited in claim 16 wherein said step h) comprises the steps of:

f1) identifying said target address as residing outside of said source address space; and

f2) resolving said target address of said target address space using said source address of said source address space.

18. The computer system as recited in claim 12 wherein said source memory region does not intersect other virtual memory regions of said source address space.

19. The computer system as recited in claim 12 wherein said source address space is a 64-bit address space.

20. The computer system as recited in claim 12 wherein no program code and no program data resides in memory locations of said source address space beyond said source base address.

21. The computer system as recited in claim 12 wherein said target memory region comprises a plurality of target memory regions and said source memory region comprises a plurality of source memory regions, such that each of said plurality of target memory regions is represented by a unique one of said plurality of source memory regions.

22. The computer system as recited in claim 12 wherein said source address space and said target address space reside in different host computers.

23. A computer-usable medium having computer-readable program code embodied therein for causing a computer system to perform the steps of:

a) reserving a target memory region (TMR) in a target address space, said TMR having a target base address;

b) reserving a source memory region (SMR) in a source address space, said SMR having a source base address;

c) generating a descriptor including information for resolving said target base address of said TMR; and

d) representing said TMR with said SMR in said source address space, said source base address being selected based on said descriptor such that said target base address can be computed from said source base address without using a lookup table.

24. The computer-usable medium as recited in claim 23 wherein said descriptor includes a virtual address representation of said target base address.

25. The computer-usable medium as recited in claim 23 wherein said source base address encodes a virtual address representation of said target base address.

26. The computer-usable medium as recited in claim 23 wherein said TMR includes a target address having an offset from said target base address, said SMR includes a source address representing said target address, and said source address encodes said offset of said target address such that said target address can be computed from said source address without using a lookup table.

27. The computer-usable medium as recited in claim 26 further comprising the steps of:

e) receiving a request to access said target address while operating in a context of said source address space; and

f) servicing said request to access said target address without using a lookup table.

28. The computer-usable medium as recited in claim 27 wherein said step h) comprises the steps of:

f1) identifying said target address as residing outside of said source address space; and

f2) resolving said target address of said target address space using said source address of said source address space.

29. The computer-usable medium as recited in claim 23 wherein said source memory region does not intersect other virtual memory regions of said source address space.

30. The computer-usable medium as recited in claim 23 wherein said source address space is a 64-bit address space.

31. The computer-usable medium as recited in claim 23 wherein no program code and no program data resides in memory locations of said source address space beyond said source base address.

32. The computer-usable medium as recited in claim 23 wherein said target memory region comprises a plurality of target memory regions and said source memory region comprises a plurality of source memory regions, such that each of said plurality of target memory regions is represented by a unique one of said plurality of source memory regions.

33. The computer-usable medium as recited in claim 23 wherein said source address space and said target address space reside in different host computers.