Power-and speed-efficient data storage/transfer architecture models and design methodologies for programmable or reusable multi-media processors

• US 6,223,274 B1
• Filed: 11/19/1998
• Issued: 04/24/2001
• Est. Priority Date: 11/19/1997
• Status: Expired due to Fees

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: De Man, Hugo, Miranda, Miguel, Janssens, Stefan, Catthoor, Francky
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/196,645
• Time in Patent Office: 887 Days
• Field of Search: 712/34, 712/35, 712/36, 712/40, 712/43, 709/108, 717/4
• US Class Current: 712/34
• CPC Class Codes: G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A programmable processing engine and a method of operating the same is described, the processing engine including a customized processor, a flexible processor and a data store commonly sharable between the two processors. The customized processor normally executes a sequence of a plurality of pre-customized routines, usually for which it has been optimized. To provide some flexibility for design changes and optimizations, a controller for monitoring the customized processor during execution of routines is provided to select one of a set of pre-customized processing interruption points and for switching context from the customized processor to the flexible processor at the interruption point. The customized processor can then be switched off and the flexible processor carries out a modified routine. By using sharable a data store, the context switch can be chosen at a time when all relevant data is in the sharable data store. This means that the flexible processor can pick up the modified processing cleanly. After the modified processing the flexible processor writes back new data into the data store and the customized processor can continue processing either where it left off or may skip a certain number of cycles as instructed by the flexible processor, before beginning processing of the new data.

Claims

1. A programmable processing engine, the processing engine including a customized processor, a flexible processor and a data store commonly sharable between the two processors, the customized processor normally executing a sequence of a plurality of pre-customized routines the programmable processing engine, comprising:

a controller for monitoring the customized processor during execution of a first code portion to select one of a set of pre-customized processing interruption points in a first routine and for switching context from the customized processor to the flexible processor at the interruption point.

2. The processing engine of claim 1, wherein the data store is at least a part of the local data storage of the customized processor.

3. The processing engine of claim 1, wherein the data store is data storage shared commonly by both the customized and the programmable processor.

4. The processing engine of claim 1, wherein the customized processor is a custom address calculation unit.

5. The processing engine of claim 1, wherein the programmable processor is an application specific instruction set processor.

6. The processing engine of claim 1, wherein the customized processor is a memory management unit.

7. The processing engine of claim 1, wherein the programmable processor includes a counter means for determining the timing of the context switch.

8. The processing engine of claim 1, wherein the customized processor is adapted supply information to the programmable processor sufficient to determine the timing of the context switch.

9. The processing engine of claim 8, wherein the programmable processor is adapted to monitor the branch evolution in the customized processor.

10. The processing engine of claim 8, wherein the programmable processor has a register and the customized processor is adapted to transmit information relating to the status of routines running on the custom processor for storage in said registers.

11. The processing engine of claim 1, wherein the flexible processor comprises a hierarchy of cache memories, the cache memories being flexibly configurable at run time.

12. The processing engine of claim 11, wherein the flexibly configurable cache memories include flexible bypasses over a selectable combination of cache levels of the hierarchy.

13. The processing engine of claim 11, wherein the flexibly configurable cache memories include means for allowing signals to reside in a selectable one of the cache levels of the hierarchy for more than one cycle.

14. The processing engine of claim 11, wherein the flexibly configurable cache memories include means for allowing different cache levels of the cache memory hierarchy to be merged in a single memory such that the size of each cache level is selectable therefrom.

15. The processing engine of claim 11, wherein the flexibly configurable cache memories include means for dividing the cache into banks and means for selectably combining the banks into selectably accessible cache partitions.

16. The processing engine of claim 11, wherein the flexibly configurable cache memories include means for allowing selection of the degree of associativity for any cache level.

17. The processing engine of claim 1, wherein access of the flexible processor to the sharable data store is provide by a switching network.

18. The processing engine of claim 17, wherein the switching network is adapted so that it only provides access to the data store at the context switch and outside the context switch the flexible and/or the customized processor is not loaded capacitively by the access connections.

19. A method of operating a programmable processing engine, the processing engine including a customized processor, a flexible processor and a data store commonly sharable between the two processors, the customized processor normally executing a sequence of a plurality of pre-customized routines the method, comprising:

monitoring the customized processor during execution of a first code portion to select one of a set of pre-customized processing interruption points in the first routine; and

switching context from the customized processor to the flexible processor at the interruption point.

20. The method of claim 19, additionally comprising:

executing a second code portion on said flexible processor using at least part of first data left in the data store by the execution of the first code portion on the customized processor.

21. The method according to claim 20, additionally comprising:

completing the execution of the second code portion on the flexible processor such that second data is left in the data store; and

switching context to the customized processor and continuing processing of a third code portion on the customized processor using at least a part of the second data.

22. The method of claim 21, wherein the flexible processor instructs the customized processor to skip a certain number of processing steps before the customized processor begins processing of the second data.

23. The method of claim 19, wherein the customized processor is powered down after the context switch to the flexible processor.

24. The method of claim 19, wherein the data store is at least a portion of the local data storage of the customized processor.

25. The method of claim 19, wherein the data store is data storage shared commonly by both the customized and the programmable processor.

26. A customized processor comprising a controller for monitoring the execution of a process running on the customized processor and being adapted to select one of a set of pre-customized processing interruption points in the process and for halting the customized processor at any one of the interruption points.

27. The customized processor of claim 26, wherein the customized processor is a custom address calculation unit.

28. The customized processor of claim 26, wherein the customized processor is a memory management unit.

29. The customized processor of claim 26, wherein the customized processor is adapted to output information sufficient to determine the timing of the context switch.

30. The customised processor according to claim 26, additionally comprising at least one switch for selectably allowing access to a part of the data storage local to the customized processor.