Method of fabricating vacuum micro-structure

• US 6,225,145 B1
• Filed: 09/07/1999
• Issued: 05/01/2001
• Est. Priority Date: 09/07/1998
• Status: Expired due to Term

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Choi, Chang Auck, Lee, Jong Hyun, Jang, Won Ick, Kim, Dae Yong
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/390,850
• Time in Patent Office: 602 Days
• Field of Search: 438/120, 438/127
• US Class Current: 438/120
• CPC Class Codes: B81B 2207/096 through the substrate
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]

Abstract

Provided is a method of fabricating a vacuum micro-structure, which is used for an element operating in a vacuum, the method comprising the steps of: (1) entirely etching an epitaxial layer of a silicon substrate having an SOI structure including an upper silicon epitaxial layer, an interlevel insulating layer and a lower silicon bulk layer to form two electrode structures and a floating vibratory structure, and encapsulating them with a vacuum sealing substrate in a vacuum; and (2) etching the silicon substrate having the SOI stricture from the back side to the interlevel insulating layer to open the electrode structures, and forming a metal electrode.

Claims

1. A method of fabricating a vacuum micro-structure, which is used for an element operating in a vacuum, the method comprising the steps of:

(1) entirely etching an epitaxial layer of a silicon substrate having an SOI structure including an upper silicon epitaxial layer, an interlevel insulating layer and a lower silicon bulk layer to form two electrode structures and a floating vibratory structure, and encapsulating them with a vacuum sealing substrate in a vacuum; and

(2) etching the silicon substrate having the SOI structure from the back side to the interlevel insulating layer to open the electrode structures, and forming a metal electrode.

2. The method as claimed in claim 1, wherein the metal electrode of the completed vacuum micro-structure in use is electrically connected to an IC chip or an external substrate for connection with external circuits via a bonding metal wire.

3. The method as claimed in claim 1, wherein the metal electrode of the completed vacuum micro-structure in use is electrically connected to an external substrate via a flip bonding metal ball.

4. The method as claimed in claim 1, wherein the step (1) comprises the steps of:

(a) etching the epitaxial layer by using a first oxide layer at both ends of the epitaxial layer of the SOI structure as a mask and removing the oxide layer to form a vacuum sealing projection;

(b) forming a second oxide layer on the whole surface of the result of step (1), defining a pattern of comb-like electrode and vibratory structures by lithography, and etching the lower bulk layer of the SOI structure by lithography in order to align the patterns with an electrode to be formed on the epitaxial layer, thereby forming an imprinting pattern;

(c) vertically etching the epitaxial layer by plasma technique using the second oxide layer as a mask; and

(d) removing the interlevel insulating layer used as a scarifying layer underlying the vibratory structure to form the floating vibratory structure, and bonding with the vacuum sealing substrate hermetically.

5. The method as claimed in claim 4, wherein in the step

(b), the imprinting pattern is formed by lithography using a both-sided aligned.

6. The method as claimed in claim 4, wherein the interlevel insulating layer used as a scarifying layer is removed by gas phase etching (GPE).

7. The method as claimed in claim 4, wherein the vacuum sealing substrate is hermetically bonded by anodic bonding in a high vacuum chamber.

8. The method as claimed in claim 1, wherein the step (2) comprises the steps of:

(a) depositing a silicon nitride layer underlying the lower silicon bulk layer to open a contact window for bonding the electrode structures, and etching the contact window region by lithography;

(b) etching down to the interlevel insulating layer underlying the electrode structures by using the remaining silicon nitride layer as a mask to open the electrode structures

(c) depositing a third oxide layer for insulation between the opened electrode structures and the external substrate; and

(d) etching the third oxide layer by lithography to open the electrode structures again, and forming an aluminum metal electrode.

9. The method as claimed in claim 8, wherein in the step (b), the lower silicon bulk layer is etched in the crystallization direction of the silicon substrate to have a deep slanting structure with an KOH etching solution by using the silicon nitride layer as a mask, and the interlevel insulating layer is etching by an ion-reactive plasma method.