Semiconductor device having triple-well
First Claim
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1. A method of forming a semiconductor device comprising:
- forming a first mask pattern for defining a first well region on a semiconductor substrate of a first conductivity type;
using said first mask pattern and large tilted-implanting impurity ions of a second conductivity type into said semiconductor substrate having a predetermined orient angle in the middle of circulation thereof to form a first well isolation region;
using said first mask pattern again and implanting impurity ions of a first conductivity type into said substrate to form a first well region as to be overlaid on a portion of said first well isolation region;
removing said first mask pattern;
forming a second mask pattern for defining a second well region on the semiconductor substrate;
using said second mask pattern and implanting impunity ions of a first conductivity type to form a second well region as to be spaced apart from said first well region;
removing said second mask pattern;
forming a third mask pattern for defining a third well region on said substrate outside of said first and second well regions; and
using said third mask and implanting impurity ions of a second conductivity type to form a third well region surrounding at least both sidewalls of said first well region.
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Abstract
The triple-well according to the present invention reduces a photo process forming a well isolation region which is used in a method for forming a prior well. That is, two times of photo processes are reduced to be one time, thereby simplifying a method for forming a triple-well of the DRAM device and reducing time and expenditure.
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Citations
3 Claims
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1. A method of forming a semiconductor device comprising:
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forming a first mask pattern for defining a first well region on a semiconductor substrate of a first conductivity type;
using said first mask pattern and large tilted-implanting impurity ions of a second conductivity type into said semiconductor substrate having a predetermined orient angle in the middle of circulation thereof to form a first well isolation region;
using said first mask pattern again and implanting impurity ions of a first conductivity type into said substrate to form a first well region as to be overlaid on a portion of said first well isolation region;
removing said first mask pattern;
forming a second mask pattern for defining a second well region on the semiconductor substrate;
using said second mask pattern and implanting impunity ions of a first conductivity type to form a second well region as to be spaced apart from said first well region;
removing said second mask pattern;
forming a third mask pattern for defining a third well region on said substrate outside of said first and second well regions; and
using said third mask and implanting impurity ions of a second conductivity type to form a third well region surrounding at least both sidewalls of said first well region. - View Dependent Claims (2, 3)
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Specification
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Current AssigneeConversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
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Original AssigneeSamsung Electronics Co. Ltd.
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InventorsLee, Beung-Keun, Kim, Byung-Kee, Hwang, Doo-Hyun, Han, Jae-Jong
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Primary Examiner(s)Mulpuri, Savitri
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Application NumberUS09/348,381Time in Patent Office664 DaysField of Search438/514, 438/525, 438/526, 438/527, 438/224, 438/228US Class Current438/525CPC Class CodesH01L 21/761 PN junctionsH10B 12/09 with simultaneous manufactu...
