Method to deposit a copper seed layer for dual damascene interconnects
First Claim
1. A method to deposit a copper seed layer for electroless copper plating in the fabrication of dual damascene interconnects in the manufacture of an integrated circuit device comprising:
- providing a dielectric layer overlying a semiconductor substrate;
patterning said dielectric layer to form trenches for planned dual damascene interconnects;
depositing a barrier layer overlying said dielectric layer;
depositing a copper seed layer overlying said barrier layer wherein said depositing is by reacting CuF2(copper(II)Fluoride) gas with said barrier layer; and
performing said electroless copper plating using said copper seed layer to complete said integrated circuit device.
1 Assignment
0 Petitions
Accused Products
Abstract
A new method of depositing a copper seed layer in the manufacture of an integrated circuit device has been achieved. The copper seed layer is thin and conformal and well-suited for subsequent electroless plating of copper. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer comprising tantalum, titanium, or tungsten is deposited overlying the dielectric layer to line the vias and trenches. A copper seed layer is deposited overlying the barrier layer by the reaction of CuF2 vapor with the barrier layer, and the integrated circuit is completed.
53 Citations
20 Claims
-
1. A method to deposit a copper seed layer for electroless copper plating in the fabrication of dual damascene interconnects in the manufacture of an integrated circuit device comprising:
-
providing a dielectric layer overlying a semiconductor substrate;
patterning said dielectric layer to form trenches for planned dual damascene interconnects;
depositing a barrier layer overlying said dielectric layer;
depositing a copper seed layer overlying said barrier layer wherein said depositing is by reacting CuF2(copper(II)Fluoride) gas with said barrier layer; and
performing said electroless copper plating using said copper seed layer to complete said integrated circuit device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
depositing a barrier compound layer overlying said semiconductor substrate prior to said step of depositing said barrier layer wherein said barrier compound layer comprises on of the group containing;
tantalum-containing compounds, titanium-containing compounds, and tungsten-containing compounds.
-
-
9. A method to deposit a copper seed layer for electroless copper plating in the fabrication of dual damascene interconnects in the manufacture of an integrated circuit device comprising:
-
providing a dielectric layer overlying a semiconductor substrate;
patterning said dielectric layer to form trenches for planned dual damascene interconnects;
depositing a barrier layer overlying said dielectric layer wherein said barrier layer comprises one of the group containing;
tantalum, titanium, and tungsten;
depositing a copper seed layer overlying said barrier layer wherein said depositing is by reacting CuF2(copper(II)Fluoride) gas with the barrier layer; and
performing said electroless copper plating using said copper seed layer to complete said integrated circuit device. - View Dependent Claims (10, 11, 12, 13, 14, 15)
depositing a barrier compound layer overlying said semiconductor substrate prior to said step of depositing said barrier layer wherein said barrier compound layer comprises on of the group containing;
tantalum-containing compounds, titanium-containing compounds, and tungsten-containing compounds.
-
-
16. A method to deposit a copper seed layer for electroless copper plating in the fabrication of dual damascene interconnects in the manufacture of an integrated circuit device comprising:
-
providing a dielectric layer overlying a semiconductor substrate;
patterning said dielectric layer to form trenches for planned dual damascene interconnects;
depositing a barrier layer overlying said dielectric layer wherein said barrier layer comprises one of the group containing;
tantalum, titanium, and tungsten;
depositing a copper seed layer overlying said barrier layer wherein said depositing is by reacting CuF2(copper(II)Fluoride) gas with the barrier layer wherein said depositing is with a plasma assist comprising;
radio frequency energy of about 13.56 MHz at a power of between about 100 Watts and 3000 Watts; and
performing said electroless copper plating using said copper seed layer to complete said integrated circuit device. - View Dependent Claims (17, 18, 19, 20)
depositing a barrier compound layer overlying said semiconductor substrate prior to said step of depositing said barrier layer wherein said barrier compound layer comprises on of the group containing;
tantalum-containing compounds, titanium-containing compounds, and tungsten-containing compounds.
-
Specification