Non-uniform gate/dielectric field effect transistor
First Claim
Patent Images
1. A transistor comprising:
- a semiconductor substrate;
a source region and a drain region formed within the semiconductor substrate;
a channel region defined within the semiconductor substrate extending between the source region and the drain region;
a gate dielectric layer formed on the substrate above the channel region, the gate dielectric layer having a non-uniform thickness along a length of the channel region; and
a gate material layer formed above the gate dielectric layer;
wherein the transistor is an N-type metal-oxide-semiconductor (NMOS) transistor, and the thickness of the gate dielectric layer decreases along the channel region from the source region to the drain region.
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Abstract
A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.
115 Citations
21 Claims
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1. A transistor comprising:
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a semiconductor substrate;
a source region and a drain region formed within the semiconductor substrate;
a channel region defined within the semiconductor substrate extending between the source region and the drain region;
a gate dielectric layer formed on the substrate above the channel region, the gate dielectric layer having a non-uniform thickness along a length of the channel region; and
a gate material layer formed above the gate dielectric layer;
wherein the transistor is an N-type metal-oxide-semiconductor (NMOS) transistor, and the thickness of the gate dielectric layer decreases along the channel region from the source region to the drain region.
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2. A transistor comprising:
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a semiconductor substrate;
a source region and a drain region formed within the semiconductor substrate;
a channel region defined within the semiconductor substrate extending between the source region and the drain region;
a gate dielectric layer formed on the substrate above the channel region, the gate dielectric layer having a non-uniform thickness along a length of the channel region; and
a gate material layer formed above the gate dielectric layer;
wherein the transistor is an P-type metal-oxide-semiconductor (PMOS) transistor, and the thickness of the gate dielectric layer decreases along the channel region from the source region to the drain region.
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3. A transistor comprising:
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a semiconductor substrate;
a source region and a drain region formed within the semiconductor substrate;
a channel region defined within the semiconductor substrate extending between the source region and the drain region;
a gate dielectric layer formed on the substrate above the channel region, the gate dielectric layer having a non-uniform thickness along a length of the channel region; and
a gate material layer formed above the gate dielectric layer;
wherein a thickness of the gate dielectric layer towards a center of the channel region is greater than a thickness of the gate dielectric layer towards the ends of the channel region.
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4. A transistor comprising:
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a semiconductor substrate;
a source region and a drain region formed within the semiconductor substrate;
a channel region defined within the semiconductor substrate extending between the source region and the drain region;
a gate dielectric layer formed on the substrate above the channel region, the gate dielectric layer having a non-uniform dielectric constant along the length of the channel region; and
a gate material layer formed above the gate dielectric layer. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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11. A transistor comprising:
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a semiconductor substrate;
a source region and a drain region formed within the semiconductor substrate;
a channel region defined within the semiconductor substrate extending between the source region and the drain region;
a gate dielectric layer formed on the substrate above the channel region, the gate dielectric layer having at least one of a non-uniform thickness and a non-uniform dielectric constant along a length of the channel region; and
a gate material layer formed above the gate dielectric layer;
wherein the gate dielectric layer comprises a plurality of different gate dielectric materials disposed adjacent each other along the channel. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A transistor comprising:
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a semiconductor substrate;
a source region and a drain region formed within the semiconductor substrate;
a channel region defined within the semiconductor substrate extending between the source region and the drain region;
a gate dielectric layer formed on the substrate above the channel region, the gate dielectric layer having at least one of a non-uniform thickness and a non-uniform dielectric constant along a length of the channel region; and
a gate material layer formed above the gate dielectric layer;
wherein a work function of the gate material layer is non-uniform along the channel. - View Dependent Claims (20, 21)
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Specification