Chip-on-chip interconnections of varied characteristics

• US 6,225,699 B1
• Filed: 06/26/1998
• Issued: 05/01/2001
• Est. Priority Date: 06/26/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sprogis, Edmund Juris, Ference, Thomas George, Howell, Wayne John
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US09/105,477
• Time in Patent Office: 1,040 Days
• Field of Search: 257/777, 257/685, 257/737, 257/778
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate

Abstract

Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (e.g., a second height greater than the first height). The first and second characteristics of the chip-on-chip interconnections allow for chip-on-chip connections to other packages, substrates or chips of different levels and/or compositions.

Claims

1. A device comprising:

a first chip;

a second chip, wherein the second chip has a chip-thickness;

a first chip-on-chip interconnection, said first chip-on-chip interconnection having a first characteristic; and

a second chip-on-chip interconnection on a same joining plane of said first chip-on-chip interconnection, said second chip-on-chip interconnection having a second characteristic,

wherein said first chip-on-chip interconnection joins said first chip to said second chip on said same joining plane forming a chip-on-chip structure;

wherein said first characteristic is a first height and said second characteristic is a second height, wherein said second height is greater than said first height; and

wherein the second height is not less than a sum of the chip-thickness and the first height.

2. The device of claim 1, wherein said second chip-on-chip interconnection joins said chip-on-chip structure to a planar surface of at least one of a package, substrate, a third chip, and a second device.

3. The device of claim 1, wherein said first characteristic further comprises a first composition and said second characteristic further comprises a second composition.

4. The device of claim 1, wherein at least one of said first chip-on-chip interconnection and said second chip-on-chip interconnection are plated.

5. The device of claim 1, wherein at least one of said first chip-on-chip interconnection and said second chip-on-chip interconnection includes at least one of a solder ball interconnection and a controlled collapse chip connection.

6. The device of claim 1, wherein at least one of said first chip-on-chip interconnection and said second chip-on-chip interconnection is a solder column.

7. The device of claim 1, wherein said first chip-on-chip interconnection is a controlled collapse chip connection.

8. The device of claim 1, wherein said second chip-on-chip interconnection is a controlled collapse chip connection.

9. A device comprising:

a first chip;

a second chip;

a first chip-on-chip interconnection having a first composition; and

a second chip-on-chip interconnection on a same joining plane of said first chip-on-chip interconnection, said second chip-on-chip interconnection having a second composition,

wherein said first chip-on-chip interconnection joins said first chip to said second chip on said same joining plane forming a chip-on-chip structure.

10. The device of claim 9, wherein said second chip-on-chip interconnection joins said chip-on-chip structure to a substrate.

11. The device of claim 9, wherein said second chip-on-chip interconnection joins said first chip to said second chip.

12. The device of claim 9, wherein said second chip-on-chip interconnection joins said chip-on-chip structure to a second device.

13. The device of claim 9, wherein said first chip-on-chip interconnection comprises a first height and said second chip-on-chip interconnection comprises a second height.

14. The device of claim 9, wherein said first chip-on-chip interconnection and said second chip-on-chip interconnection are plated.

15. The device of claim 9, wherein said first chip-on-chip interconnection is a solder ball interconnection.

16. The device of claim 9, wherein said first chip-on-chip interconnection is a solder column.

17. The device of claim 9, wherein said first chip-on-chip interconnection is a controlled collapse chip connection.

18. The device of claim 9, wherein said second chip-on-chip interconnection is a controlled collapse chip connection.

19. The device of claim 9, wherein said first chip-on-chip interconnection and said second chip-on-chip interconnection further differ in a characteristic selected from the group consisting of:

height, shape, and diameter.

20. A device comprising:

a first chip;

a second chip;

a first chip-on-chip interconnection, comprising a solder column, having a first characteristic; and

a second chip-on-chip interconnection on a same joining plane of said first chip-on-chip interconnection, said second chip-on-chip interconnection having a second characteristic,

wherein said first chip-on-chip interconnection joins said first chip to said second chip on said same joining plane forming a chip-on-chip structure.

21. The device of claim 20 wherein said second chip-on-chip interconnection joins said chip-on-chip structure to a substrate.

22. The device of claim 20 wherein said second chip-on-chip interconnection joins said first chip to said second chip.

23. The device of claim 20 wherein said second chip-on-chip interconnection joins said chip-on-chip structure to a second device.

24. The device of claim 20, wherein said first characteristic is a first height and said second characteristic is a second height.

25. The device of claim 20, wherein said first characteristic is a first diameter and said second characteristic is a second diameter.

26. The device of claim 20, wherein said first characteristic is a first composition and said second characteristic is a second composition.

27. The device of claim 20, wherein said first chip-on-chip interconnection and said second chip-on-chip interconnection are plated.

28. A chip-on-chip package comprising:

a plurality of devices at different levels;

a first chip-on-chip interconnection having a first composition; and

a second chip-on-chip interconnection having a second composition,

wherein said first and said second chip-on-chip interconnections connect said plurality of devices together on a same joining plane.

29. The assembly of claim 28 wherein said first interconnection further comprises a first height and a first diameter and said second interconnection further comprises a second height and a second diameter.

30. A device comprising:

a first chip;

a second chip;

a first chip-on-chip interconnection on said first chip, said first chip-on-chip interconnection having a first characteristic;

a second chip-on-chip interconnection on a same joining plane of said first chip-on-chip interconnection, said second chip-on-chip interconnection having a second characteristic,

wherein said first chip-on-chip interconnection joins said first chip to said second chip on said same joining plane forming a chip-on-chip structure;

wherein said second chip-on-chip interconnection joins said chip-on-chip structure to a planar surface;

wherein the planar surface is parallel with said joining plane; and

wherein the planar surface is continuous where it is adjacent to the first chip and the second chip.

31. The device of claim 30, wherein the planar surface is one of:

a surface of a third chip;

a surface of a package;

a surface of a substrate; and

a surface of a second device.

32. The device of claim 30, wherein at least one of said first chip-on-chip interconnection and said second chip-on-chip interconnection includes at least one of a solder ball interconnection, a solder column, and a controlled collapse chip connection.