Body voltage controlled semiconductor integrated circuit

• US 6,225,846 B1
• Filed: 06/03/1997
• Issued: 05/01/2001
• Est. Priority Date: 01/23/1997
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Wada, Yoshiki, Ueda, Kimio
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US08/867,854
• Time in Patent Office: 1,428 Days
• Field of Search: 327/215, 327/219, 327/534
• US Class Current: 327/215
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A body voltage controlled semiconductor integrated circuit which can solve a problem of a conventional CMOS inverter in that it cannot operate at a supply voltage beyond the built-in voltage of the CMOS transistors if their body electrodes are each connected to their own gate electrodes rather than to their source electrodes to quicken the operation of the CMOS inverter. A voltage divider circuit is provided which conducts during the operation of the CMOS transistors of the inverter so that the body voltages of the PMOS transistor or the NMOS transistor of the inverter is varied in the direction of reducing their threshold voltages. By controlling the size of electrodes and the voltages applied to the body electrodes of transistors constituting the voltage divider circuit, it becomes possible to operate the CMOS inverter at the supply voltage beyond the built-in voltage.

Claims

1. A body voltage controlled semiconductor integrated circuit comprising:

a first inverter including a first PMOS transistor, a first NMOS transistor, a first link interconnecting a gate electrode of said first PMOS transistor and a gate electrode of said first NMOS transistor, a second link interconnecting a drain electrode of said first PMOS transistor and a drain electrode of said first NMOS transistor;

a second inverter including a second PMOS transistor, a second NMOS transistor, a third link interconnecting a gate electrode of said second PMOS transistor and a gate electrode of said second NMOS transistor, a fourth link interconnecting a drain electrode of said second PMOS transistor and a drain electrode of said second NMOS transistor;

a voltage divider circuit including a third PMOS transistor, a third NMOS transistor, a fifth link interconnecting a drain electrode of said third PMOS transistor and a drain electrode of said third NMOS transistor, a sixth link connected to the second inverter interconnecting a gate electrode of said third PMOS transistor and a gate electrode of said third NMOS transistor, a fourth PMOS transistor which is connected between a body electrode and a source electrode of said third PMOS transistor, and which is always kept ON, a fourth NMOS transistor which is connected between a body electrode and a source electrode of said third NMOS transistor, and which is always kept ON,

wherein said fifth link is connected with said second link and said third link, the source electrode of said third PMOS transistor is connected to a body electrode of said second PMOS transistor, and the source electrode of said third NMOS transistor is connected to a body electrode of said second NMOS transistor.

2. The body voltage controlled semiconductor integrated circuit as claimed in claim 1, wherein said sixth link is connected to said fourth link.

3. The body voltage controlled semiconductor integrated circuit as claimed in claim 1, further comprising a third inverter with its input terminal connected to said second link and its output terminal connected to said sixth link.

4. A body voltage controlled semiconductor integrated circuit comprising:

a first inverter including a first PMOS transistor, a first NMOS transistor, a first link interconnecting a gate electrode of said first PMOS transistor and a gate electrode of said first NMOS transistor, a second link interconnecting a drain electrode of said first PMOS transistor and a drain electrode of said first NMOS transistor;

a second inverter including a second PMOS transistor, a second NMOS transistor, a third link interconnecting a gate electrode of said second PMOS transistor and a gate electrode of said second NMOS transistor, a fourth link interconnecting a drain electrode of said second PMOS transistor and a drain electrode of said second NMOS transistor;

a voltage divider circuit including a third PMOS transistor with its body electrode and source electrode interconnected, a third NMOS transistor with its body electrode and source electrode interconnected, a fifth link interconnecting a drain electrode of said third PMOS transistor and a drain electrode of said third NMOS transistor, a sixth link connected to the second inverter interconnecting a gate electrode of said third PMOS transistor and a gate electrode of said third NMOS transistor, a fourth PMOS transistor which is connected to the body electrode of said third PMOS transistor, and which is always kept ON, a fourth NMOS transistor which is connected to the body electrode of said third NMOS transistor, and which is always kept ON,

wherein said fifth link is connected with said second link and said third link, the source electrode of said third PMOS transistor is connected to a body electrode of said second PMOS transistor, and the source electrode of said third NMOS transistor is connected to a body electrode of said second NMOS transistor.

5. The body voltage controlled semiconductor integrated circuit as claimed in claim 4, wherein said sixth link is connected to said fourth link.

6. The body voltage controlled semiconductor integrated circuit as claimed in claim 4, further comprising a third inverter with its input terminal connected to said second link and its output terminal connected to said sixth link.

7. A circuit comprising:

an inverter circuit including a first field effect transistor having a first electrode and a second electrode and a gate electrode, and

a second field effect transistor having a first electrode, a second electrode and a gate electrode, the first electrode of said second field effect field transistor connected to the first electrode of said first field effect transistor, and the gate electrode of said second field effect transistor connected to the gate electrode of said first field effect transistor; and

a voltage dividing circuit including

a third field effect transistor having a first electrode connected to the gate electrode of said first field effect transistor, a second electrode connected to a body region of said first field effect transistor, and a gate electrode connected to the first electrode of said first field effect transistor, and

a fourth field effect transistor having a first electrode connected to the gate electrode of said second field effect transistor, a second electrode connected to a body region of said second field effect transistor and a gate electrode connected to the first electrode of said [third] second field effect transistor.

8. The circuit as claimed in claim 7, wherein

a common input signal line is connected to the gate electrodes of said first and second field effect transistors, and an output signal line is connected to a node where the first electrodes of said first and second field effect transistors are connected.

9. The circuit as claimed in claim 7, wherein each of said first and third field effect transistors is of a n-type, and each of said second and fourth field effect transistors is of a P-type.

10. The circuit as claimed in claim 7, further comprising

a fifth field effect transistor having a first electrode connected to the second electrode of said third field effect transistor, a second electrode and a gate electrode, wherein a fixed voltage is applied to the gate electrode of said fifth field effect transistor to render said fifth field effect transistor conductive.

11. The circuit as claimed in claim 7, wherein a body region of said third field effect transistor is connected to the second electrode of said fifth field effect transistor.

18. The circuit as claimed in claim 10, further comprising

a sixth field effect transistor having a first electrode connected to the second electrode of said fourth field effect transistor, a second electrode and a gate electrode, wherein another fixed voltage is applied to the gate electrode of said sixth field effect transistor to render said sixth field effect transistor conductive.

12. A circuit comprising:

a first inverter including a first field effect transistor having a first electrode, a second electrode and a gate electrode, and a second field effect transistor having a first electrode, a second electrode and a gate electrode, the first electrode of said second field effect transistor connected to the first electrode of said first field effect transistor, and the gate electrode of said second field effect transistor connected to the gate electrode of said first field effect transistor,

a voltage dividing circuit including third and fourth field effect transistors, said third field effect transistor having a first electrode connected to the gate electrode of said first field effect transistor, a second electrode connected to a body region of said first field effect transistor and a gate electrode, said fourth field effect transistor having a first electrode connected to the gate electrode of said second field effect transistor, a second electrode connected to a body region of said second field effect transistor and a gate electrode connected to the gate electrode of said third field effect transistor; and

a second inverter having an input connected to the gate electrode of said first field effect transistor and an output connected to the gate electrodes of said third and fourth field effect transistors.

13. The circuit as claimed in claim 12, wherein

each of said first and third field effect transistors is of a P-type.

14. The circuit as claimed in claim 12, wherein

each of said first and third field effect transistors is of an n-type.

15. The circuit as claimed in claim 12, wherein

each of said first and third field effect transistors is of an n-type, and each of said second and fourth field effect transistors is of a P-type.

16. The circuit as claimed in claim 12, further comprising:

a third field effect transistor having a first electrode connected to the second electrode of said second field effect transistor, a second electrode and a gate electrode, wherein a fixed voltage is applied to the gate electrode of said third field effect transistor to render said third field effect transistor conductive.

17. The circuit as claimed in claim 16, wherein

a body region of said third field effect transistor is connected to the second electrode of said fifth field effect transistor.

19. A circuit for outputting an output signal in response to an input signal, comprising:

an inverter including a) a first transistor which is a p-type field effect transistor, having a gate electrode connected to a first node, a drain electrode connected to a second node, and a source electrode to which a first voltage is applied, and b) a second transistor which is an n-type field effect transistor, having a gate electrode connected to the first node, a drain electrode connected to the second node, and a source electrode to which a second voltage is applied, the second voltage being lower than the first voltage; and

a control circuit for controlling a voltage applied to a body electrode of said first transistor and a body electrode of said second transistor in accordance with a voltage of the second node and the input signal, said control circuit including a) a third transistor receiving the input signal at a first terminal, connected to the second node at a gate terminal and connected to the body electrode of said first transistor at a second terminal, and b) a fourth transistor receiving the input signal at a first terminal connected to the second node at a gate terminal and connected to the body electrode of said second transistor at a second terminal,

wherein a voltage of the first node varies in response to the input signal and the output signal is output from the second node.

20. The circuit as claimed in claim 19, wherein

said third and fourth transistors are so configured as to be rendered complementarily conductive.

21. A circuit for outputting an output signal in response to an input signal, comprising:

a first inverter including a first transistor which is a p-type field effect transistor, having a gate electrode connected to a first node, a drain electrode connected to a second node, and a source electrode to which a first voltage is applied, and a second transistor which is an n-type field effect transistor, having a gate electrode connected to the first node, a drain electrode connected to the second node, and a source electrode to which a second voltage is applied, the second voltage being lower than the first voltage;

a second inverter for inverting a logic level of the input signal to output an inverted signal; and

a control circuit for controlling voltages applied to a body electrode of said first transistor and a body electrode of said second transistor in accordance with a voltage of the input signal and the inverted signal output from said second inverter said control circuit including a third transistor receiving the inverted signal and connected to the first node and the body electrode of said first transistor and a fourth transistor receiving the inverted signal and connected to the first node and the body electrode of said second transistor, wherein a voltage of the first node varies in response to the input signal and the output signal is output from the second node.

22. The circuit as claimed in claim 21, wherein

said third and fourth transistors are so configured as to be rendered conductive complementarily.

23. A circuit comprising:

a first inverter receiving an input signal and outputting an output signal having a logical value opposite to the input signal, including;

a first transistor which is a p-type field effect transistor, having a gate electrode connected to a first node receiving the first signal, a drain electrode connected to a second node providing the output signal and a source electrode to which a first voltage is applied, and

a second transistor which is an n-type field effect transistor, having a gate electrode connected to the first node, a drain electrode connected to the second node and a source electrode to which a second voltage is applied, the second voltage being lower than the first voltage;

a control circuit connected to a third node, for controlling voltages applied to body electrodes of said first and second transistors in accordance with a voltage of the third node, said control circuit including;

a third transistor connected to the third node and the body electrode of said first transistor, and

a fourth transistor connected to the third node and the body electrode of said second transistor; and

a second inverter connected between the first and third nodes, bring the first and third node logical values opposite to each other.

24. The circuit as claimed in claim 23, wherein said third and fourth transistors are configured to be complementarily conductive.