Series connected multi-stage linear FET amplifier circuit

• US 6,225,866 B1
• Filed: 06/14/2000
• Issued: 05/01/2001
• Est. Priority Date: 05/31/1994
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kubota, Yasushi, Shiraki, Ichiro
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US09/594,439
• Time in Patent Office: 321 Days
• Field of Search: 330/295, 330/277, 330/310, 330/311
• US Class Current: 330/295
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H03F 3/345 with field-effect devices H03F3/347 takes precedence

Abstract

A sampling circuit is arranged so that source voltages V_DD and V_EE, which are to be applied to two inverters at the latter stages in a signal path on the p-channel transistor side, are shifted to the positive side with respect to source voltages V_CC and V_SS that are applied to the other inverters. With such a power supply construction, video signals on the low-potential side in a video signal line are picked up by the n-channel transistor and video signals on the high-potential side are picked up by the p-channel transistor, and the resulting signals are supplied to a data signal line. This arrangement makes it possible to reduce the gate input voltage upon conduction of the sampling switch. Moreover, by shifting the levels of the source voltages as described above, it becomes possible to ensure writing and holding operations even in the case of having signals with a small amplitude. Therefore, even in the case when devices having low withstand voltage are used, no damage is caused on the circuit characteristics.

Claims

1. A signal amplifier comprising:

a first amplification circuit and a second amplification circuit for amplifying respective input signals almost linearly, the first and second amplification circuits being connected in parallel with each other,

wherein upon receipt of an increasing level change in the input signal, the first amplification circuit has a response speed that is greater than that of the second amplification circuit, and upon receipt of a decreasing level change in the input signal, the second amplification circuit has a response speed that is greater than that of the first amplification circuit.

2. The signal amplifier as defined in claim 1, wherein the first amplification circuit is a cascode-type linear circuit constituted of a plurality of series connected n-channel transistors of MOS type and the second amplification circuit is a cascode-type linear circuit constituted of a plurality of series connected p-channel transistors of MOS type.

3. The signal amplifier as defined in claim 1, wherein each of the first and second amplification circuits is made up of a differential amplifier that is constituted of n-channel transistors and p-channel transistors of MOS type and that is disposed at the former stage, and a source-follower circuit that is constituted of n-channel transistors and p-channel transistors of MOS type and that is disposed at the latter stage.

4. The signal amplifier as defined in claim 1, wherein:

the first amplification circuit is provided with a first linear circuit for amplifying an input signal almost linearly and a second linear circuit for amplifying an output signal from the first linear circuit almost linearly; and

the second amplification circuit is provided with a third linear circuit for amplifying an input signal almost linearly and a fourth linear circuit for amplifying an output signal from the third linear circuit almost linearly.

5. The signal amplifier as defined in claim 4, wherein:

the second linear circuit is a cascode-type linear circuit constituted of a plurality of series connected n-channel transistors of MOS type; and

the fourth linear circuit is a cascode-type linear circuit constituted of a plurality of series connected p-channel transistors of MOS type.

6. The signal amplifier as defined in claim 4, wherein each of the second and fourth linear circuits is made up of a differential amplifier that is constituted of n-channel transistors and p-channel transistors of MOS type and that is disposed at the former stage, and a source-follower circuit that is constituted of n-channel transistors and p-channel transistors of MOS type and that is disposed at the latter stage.

7. The signal amplifier as defined in claim 4, wherein the first linear circuit is constituted of p-channel transistors of MOS type and the third linear circuit is constituted of n-channel transistors of MOS type.

8. The signal amplifier as defined in claim 1, wherein the first and second amplification circuits are installed on a multi-crystal silicon thin film formed on an insulating substrate.

9. The signal amplifier as defined in claim 1, wherein the first and second amplification circuits are installed on a mono-crystal silicon thin film formed on an insulating substrate.