Encoder arrangement and bit-exact IDCT protocol

• US 6,225,923 B1
• Filed: 02/16/1999
• Issued: 05/01/2001
• Est. Priority Date: 02/19/1992
• Status: Expired due to Term

• Current Assignee: 8X8, Inc.
• Original Assignee: 8X8, Inc.
• Inventors: Andrews, D. Barry
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Jeanglaude, Jean Bruner
• Application Number:
  US09/250,891
• Time in Patent Office: 805 Days
• Field of Search: 341/94, 341/200, 341/50, 348/420, 382/233, 382/250, 708/402, 709/247
• US Class Current: 341/94
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: H04N 7/141 between two video terminals, e.g. videophone telephonic communication systems combined with television receiver for reception of entertainment or information matter H04M11/085
• CPC Class Codes: H04N 7/15 Conference systems

Abstract

The encoder arrangement and bit-exact IDCT protocol provides methods and arrangements that prevent an accumulation of errors between a transmitting codec and a receiving codec. One example embodiment is directed to an arrangement for use in a first terminal for communicating representations of images with a second terminal using a communications channel on which communication has been established between the first terminal and the second terminal. The arrangement includes a processor-based decoder/encoder circuit and a bit-exact circuit. The processor-based decoder/encoder circuit is arranged to process video data using an inverse transformer loop. The bit-exact circuit prevents unacceptable accumulation of an error within the inverse transformer loop by using the inverse transformer in the loop according to a bit-exact specification between the encoder and decoder in the respective first and second terminals.

Claims

1. A method for encoding and decoding a representation of an image for communication in a system between a first terminal to a second terminal, comprising:

operating each of the first and second terminals using an inverse transformer loop; and

preventing unacceptable accumulation of an error within the inverse transformer loop by at least one of;

using the inverse transformer in the loop according to a bit-exact specification between the encoder and decoder in the respective first and second terminals; and

using the inverse transformer in the loop according to one of a plurality of bit-exact specifications between the encoder and decoder in the respective first and second terminals and negotiating a common decision on the particular specification through encoder/decoder negotiation.

2. A decoder in one of the first and second terminals, the decoder constructed and arranged to participate in the method of claim 1.

3. An encoder in one of the first and second terminals, the encoder constructed and arranged to participate in the method of claim 1.

4. A video-conferencing terminal having a decoder and an encoder that are constructed and arranged to operate according to claim 1.

5. An arrangement for transmitting a representation of an image from a first terminal to a second terminal using a communications channel on which communication has been established between the first terminal and the second terminal, comprising:

means for operating each of the first and second terminals using an inverse transformer loop; and

means for preventing unacceptable accumulation of an error within the inverse transformer loop by at least one of;

using the inverse transformer in the loop according to a bit-exact specification between the encoder and decoder in the respective first and second terminals; and

using the inverse transformer in the loop according to one of a plurality of bit-exact specifications between the encoder and decoder in the respective first and second terminals and negotiating a common decision on the particular specification through encoder/decoder negotiation.

6. An arrangement for use in a first terminal for communicating representations of images with a second terminal using a communications channel on which communication has been established between the first terminal and the second terminal, comprising:

a processor-based decoder/encoder circuit arranged to process video data using an inverse transformer loop; and

a circuit for preventing unacceptable accumulation of an error within the inverse transformer loop by at least one of;

using the inverse transformer in the loop according to a bit-exact specification between the encoder and decoder in the respective first and second terminals; and

using the inverse transformer in the loop according to one of a plurality of bit-exact specifications between the encoder and decoder in the respective first and second terminals and negotiating a common decision on the particular specification through encoder/decoder negotiation.