Dot clock recovery method and apparatus

• US 6,226,045 B1
• Filed: 10/31/1997
• Issued: 05/01/2001
• Est. Priority Date: 10/31/1997
• Status: Expired due to Fees

• Current Assignee: Hitachi America Limited (Hitachi, Ltd.)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Vidovich, Nikola
• Primary Examiner(s): Harvey, David E.
• Application Number:
  US08/960,539
• Time in Patent Office: 1,278 Days
• Field of Search: 348/537, 348/572, 348/574, 348/573, 348/500, 348/536, 348/538, 348/539, 341/158
• US Class Current: 348/539
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H04N 9/44 Colour synchronisation

Abstract

The present invention overcomes the problem of image detail timing jitters in flat panel display devices by compensating for the phase difference between the dot clock derived by the Horizontal-sync signal and the display data. This is done by providing an apparatus and method for detecting the phase difference between the red, green and blue signal transitions and the dot clock signal that has been regenerated from the Horizontal sync signal. The detected phase difference is then applied, in a feedback fashion, to synchronize the dot clock phase with the signal transitions.

Claims

1. A digital display device having an apparatus for applying phase differences between red, green and blue signal transitions in analog video signals to a phase of a dot clock signal that has been regenerated from a horizontal synchronization signal in order to synchronize display of image data, said apparatus comprising:

a differentiator for receiving the analog video signal and extracting signal transitions from the red, green and blue components of the video signal;

a pulse shaper for eliminating amplitude variations in the signal transitions;

a phase detector for detecting the phase measurements of the signal transitions between the red, green and blue components of the video signal, and for generating a sampling signal representative of phase differences of each of the signal transitions;

a sample and hold means for converting the sampling signal from a first analog signal into a digital signal, and then converting the digital signal into a second analog signal after a preset time period;

a phase shifter for combining said second analog signal with the horizontal synchronization signal to adjust the phase of the horizontal synchronization signal and generate a clock signal in phase with said signal transitions in the video signal, wherein said clock signal is used by the display device to synchronize display image data.

2. A digital display device having an apparatus for processing analog video signals according to claim 1, further comprising a storage register for storing said first analog signal after it is converted into a digital signal.

3. A digital display device having an apparatus for processing analog video signals according to claim 1, further comprising an amplifier for amplifying said second analog signal.

4. A digital display device having an apparatus for processing analog video signals according to claim 1, further comprising a first divider circuit coupled to said first phase detector means for processing a plurality of dot clock signals by said first phase detector means.

5. A digital display device having an apparatus for processing analog video signals according to claim 1, further comprising a second phase detector means for detecting the phase measurements of the horizontal synchronization signal before it is combined with said second analog signal at said phase shifter.

6. A digital display device having an apparatus for processing analog video signals according to claim 5, further comprising a second divider circuit coupled to said second phase detector means for processing a plurality of image formats by said second phase detector means.

7. A method of synchronizing display of video image signals with a clock signal by applying phase differences between red, green and blue signal transitions in analog video signals to a phase of a horizontal synchronization signal, said method comprising:

extracting signal transitions from the red, green and blue components of the video signal;

detecting phase measurements of the signal transitions between the red, green and blue components of the video signal;

generating a sampling signal representative of phase differences of each of the signal transitions; and

combining the phase differences of said sampling signal with the phase of the horizontal synchronization signal to adjust the phase of the horizontal synchronization signal and generate a clock signal in phase with said signal transitions in the video signal, and thereby synchronize display image data with the generated clock signal.

8. A method of synchronizing the display of video image signals according to claim 7 further comprises removing amplitude variations in the signal transitions after the red, green and blue components are extracted from the video signal.

9. A method of synchronizing the display of video image signals according to claim 7 further comprises converting the sampling signal from a first analog signal into a digital signal, and then converting the digital signal into a second analog signal after a preset time period.

10. A method of synchronizing the display of video image signals according to claim 7, further comprises storing said first analog signal after it is converted into a digital signal.

11. A method of synchronizing the display of video image signals according to claim 7, further comprises amplifying said second analog signal.

12. A method of synchronizing the display of video image signals according to claim 7, further comprises processing a plurality of dot clock signals when detecting the phase measurements of the signal transitions between the red, green and blue components of the video signal.

13. A method of synchronizing the display of video image signals according to claim 7 further comprises detecting the phase measurements of the horizontal synchronization signal before it is combined with sampling signal.

14. A method of synchronizing the display of video image signals according to claim 13, further comprises processing a plurality of image formats when detecting the phase measurements of the horizontal synchronization signal before it is combined with the sampling signal.

15. A method of synchronizing the display of video image signals according to claim 9 further comprises detecting the phase measurements of the horizontal synchronization signal before it is combined with said second analog signal.

16. A method of synchronizing the display of video image signals according to claim 15, further comprises processing a plurality of image formats when detecting the phase measurements of the horizontal synchronization signal before it is combined with said second analog signal.

17. An apparatus for synchronizing the display of image data with a dot clock signal that has been regenerated from a horizontal synchronization signal, said apparatus comprising:

a plurality of capacitors for receiving an analog video signal and extracting signal transients from the red;

green and blue components of the video signal;

a comparator for eliminating amplitude variations in the signal transients;

a voltage sampling means for generating a sampling signal representative of phase differences of each of the signal transients;

a signal conversion means for converting the sampling signal between analog and digital domains; and

a phase shifter means for combining said converted sampling signal with the horizontal synchronization signal to adjust the phase of the horizontal synchronization signal and to generate a clock signal in phase with said signal transients in the video signal, to thereby synchronize display image data.

18. An apparatus for synchronizing the display of image data with a dot clock signal according to claim 17, wherein said comparator is a high speed limiter circuit.

19. An apparatus for synchronizing the display of image data with a dot clock signal according to claim 17, further comprising a low pass filtering means for providing frequency or noise filtering.

20. An apparatus for synchronizing the display of image data with a dot clock signal according to claim 19, further comprising an amplifier for amplifying the filtered signal.

21. An apparatus for synchronizing the display of image data with a dot clock signal according to claim 19, further comprising a delay controller coupled to said low pass filtering means and said phase shifter means for controlling a delay that said phase shifter means applies to the horizontal synchronization signal.

22. An apparatus for synchronizing the display of image data with a dot clock signal according to claim 21, further comprising a time interval measurement circuit coupled to said phase shifter means to measure time intervals between signal transients.

23. A digital display device having an apparatus for applying phase differences between the red, green and blue signal transitions in analog video signals in a feedback manner to a phase of a dot clock signal that has been regenerated from a horizontal synchronization signal, to synchronize display of image data including a differentiator for receiving an analog video signal and extracting signal transitions from the red, green and blue components of the video signal;

means for eliminating amplitude variations in the signal transitions;

a phase detector circuit for detecting phase measurements of the signal transitions between the red, green and blue components of the video signal, and for generating a sampling signal representative of the phase differences of each of the signal transitions;

a sample and hold circuit for converting the sampling signal from a first analog signal into a digital signal, and then converting the digital signal into a second analog signal after a preset time period; and

a phase shifter for combining said second analog signal with the horizontal synchronization signal to adjust the phase of the dot clock signal, the phase adjusted clock signal then being used by the display device to synchronize display image data and present a jitter-free screen image.

24. A method for eliminating image detail timing jitters in digital display devices by compensating for a phase difference between a dot clock derived by a horizontal-sync signal and display data, comprising receiving an analog video signal containing red, green and blue signal transitions, adding the signal transitions together, evening out amplitude variations before phase differences of each of the signal transitions is measured, establishing a sampling signal representative of the phase differences between the signal transitions, converting the sampling signal into the digital domain, holding the sampling signals for a period of time, converting the sampling signal back to the analog domain as a second analog signal, and the second analog signal is used in a feedback fashion to control the phase of a dot clock signal that has been regenerated from the horizontal sync signal, thereby eliminating timing jitters.