Semiconductor memory device having reduced data access time and improve speed

• US 6,226,215 B1
• Filed: 12/29/1999
• Issued: 05/01/2001
• Est. Priority Date: 12/30/1998
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Yoon, Ha Ryong
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Yoha, Connie C.
• Application Number:
  US09/473,698
• Time in Patent Office: 489 Days
• Field of Search: 365/185.25, 365/230.03, 365/203
• US Class Current: 365/230.03
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Disclosed is a semiconductor memory device comprising a precharging unit between bit lines within a memory cell region and bit lines within a sense amplifier region, respectively. When performing a column operation on the bit lines within the sense amplifier region upon consecutive read operations, the bit lines within the memory cell region are precharged and a wordline is disabled, and thus the memory cell region comes to the ready to enable a new wordline. Accordingly, the timing of row and column operations can be reduced, thereby reducing a data access time and realizing a high speed operation.

Claims

1. In a semiconductor memory device comprising:

a unit memory cell;

a first line connecting means responsive to a first bit line separating signal for connecting or disconnecting bit lines within the unit memory cell region and bit lines within a sense amplifier region;

a second line connecting means responsive to a second bit line separating signal for connecting or disconnecting bit lines within an other unit memory cell region and bit lines within the sense amplifier region;

a first precharging means for equalizing and precharging the bit lines within the sense amplifier region under a control by a first precharging control signal;

a bit line sense amplifier connected between the bit lines within the sense amplifier region for performing a bit line sensing operation under a control by sense amplifier control signals; and

a data bus line connecting means responsive to a column selecting signal for connecting or disconnecting the bit lines within the sense amplifier region and data bus lines being characterized in that;

said semiconductor memory device further includes a second precharging means for equalizing and precharging said bit lines within the unit memory cell region under a control by a second precharging control signal;

wherein said first and second bit line separating signals are generated from a bit line separating signal generating means in accordance with a bank selecting signal and a sensing generating signal;

said first bit line precharging control signal is generated from a first precharging control means in accordance with said bank selecting signal and said first and second bit line separating signals; and

said second bit line precharging control signal is generated from a second precharging control means in accordance with said bank selecting signal and a /CAS signal.

2. A semiconductor memory device according to claim 1, wherein said bit line separation signal generating means includes:

an enabling means for enabling said bit line separation signals upon receipt of said bank selection signal generated in accordance with a /RAS signal;

a delay means for delaying for a predetermined time the sensing generating signal generating said sense amplifier control signals; and

a disabling means for disabling the bit line separation signals using the sense generation signal.

3. A semiconductor memory device according to claim 2, wherein the predetermined time in said delay means is a time required for separating enough the bit lines so that data can be rewritten in the memory cell.

4. A semiconductor memory device according to claim 1, wherein said first precharging control means includes:

a first inverter for inverting said bank selection signal applied thereto;

a NOR gate for NORing said bit line separation signals and the output signal of said first inverter;

a NAND gate for NANDing said bit line separation signals and the output signal of said first inverter;

a D Flip-Flop for receiving the output signal of said NAND gate as a clock input and the output signal of said NOR gate as a data input and for latching the signals for a predetermined time;

a negative AND gate for receiving the respective inverted signals of said bank selection signal and said bit line separation signals and for ANDing them; and

a T Flip-Flop setting by the output signal of said negative AND gate and generating said first precharging control signal by toggling in accordance with the output signal of said D Flip-Flop.

5. A semiconductor memory device according to claim 1, wherein said second precharging control means includes:

first and second pulse generating means for generating pulse signals respectively using said /CAS signal and said bank selection signal;

an output driving means being switched by said respective pulse control signals generated from said first and second pulse generating means and adjusting the potential of the output terminal;

a latch means for latching the potential of said output terminal; and

a buffer means for buffering the output potential of said latch means.

6. A semiconductor memory device according to claim 5, wherein said first pulse generating means includes:

an odd number of inverters connected in serial for inverting and delaying said /CAS signal; and

a NAND gate for combining the output signal of the last inverter of said inverters and said /CAS signal.

7. A semiconductor memory device according to claim 5, wherein said second pulse generating means includes:

an odd number of inverters connected in serial for inverting and delaying said bank selection signal;

a NAND gate for combining the output signal of the last inverter said inverters and said bank selection signal; and

a inverter for inverting the output signal of said NAND gate.

8. A semiconductor memory device according to claim 5, wherein said output driving means includes:

a PMOS transistor and a NMOS transistor being connected in serial between a power supply voltage and a ground voltage and having their respective gates receiving pulse signals generated from said first and second pulse generating means.

9. A semiconductor memory device according to claim 5, wherein said latch means includes:

an inverter for inverting the potential of said output terminal; and

a PMOS transistor being connected between a power supply voltage and said output terminal and having its gate terminal to which the output signal of said inverter is feedback.