Analog receive equalizer for digital-subscriber-line communications system

• US 6,226,322 B1
• Filed: 03/30/1998
• Issued: 05/01/2001
• Est. Priority Date: 03/30/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mukherjee, Subahashish
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): Tran, Khai
• Application Number:
  US09/050,620
• Time in Patent Office: 1,128 Days
• Field of Search: 375/222, 375/229, 375/233, 333/28 R, 333/172, 330/293, 330/304, 330/101, 330/94, 330/92, 330/82, 330/87, 330/260, 708/323
• US Class Current: 375/229
• CPC Class Codes: H04B 3/145 variable equalisers
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 27/0002 analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143
• CPC Class Codes: H04L 5/023 Multiplexing of multicarrier modulation signals multicarrier modulation H04L27/2601

Abstract

Digital subscriber modems (8, 15) for use in Asynchronous Digital Subscriber Line (ADSL) communications are disclosed. Each modem includes a digital transceiver function (10, 13) and an analog front end function (10, 11), where the analog front end function (10, 11) is integrated into a single integrated circuit. According to the disclosed embodiments, the analog front end functions (10, 11) each include a transmit and a receive side. The transmit side includes oversampled registers (44C, 44R) and digital filters (46C, 46R) which serve to increase the sample rates of the digital data to be transmitted, so that the analog-to-digital converter (48C, 48R) operates in an oversampled manner, and so that the downstream analog low pass filters (50C, 50R) can be realized with relatively simple, low-order filters. On the receive side, digital filter functions (64C, 64R) are included downstream from the analog-to-digital converters (62C, 62R), to minimize the complexity of the receive-side analog filters (58C, 58R). The remote DSL modem (8) also includes an equalizer function (57) to boost the signal amplitude with increasing frequency, to overcome the effects of line attenuation on the high frequency downstream transmissions.

Claims

1. A receive equalizer circuit, comprising:

a first stage, comprising;

a first operational amplifier, having an input and an output;

a first input impedance network, coupled between an input of the receive equalizer circuit and the input of the first operational amplifier, having an impedance selected from one of a first plurality of input impedance values to define a first dominant zero in a frequency characteristic of the receive equalizer circuit, and comprised of a capacitor and a variable resistance connected in parallel with the capacitor; and

a first feedback impedance network, coupled between the output and the input of the first operational amplifier, and having an impedance selected from one of a first plurality of feedback impedance values and that is comprised of a capacitor and a variable resistance connected in parallel with the capacitor; and

a second stage, comprising;

a second operational amplifier, having an input, and an output;

a second input impedance network, coupled between the output of the first operational amplifier and the input of the second operational amplifier, to define a second dominant zero in the frequency characteristic of the receive equalizer circuit; and

a second feedback impedance network, coupled between the output and the input of the second operational amplifier;

wherein each of the variable resistances comprise a plurality of resistors connected in parallel with one another, each of the plurality of resistors capable of being selectably enabled and disabled.

2. The receive equalizer circuit of claim 1, wherein the second input impedance network has an impedance selected from one of a second plurality of input impedance values;

and wherein the second feedback impedance network has an impedance selected from one of a second plurality of feedback impedance values.

3. The receive equalizer circuit of claim 2, wherein each of the second input impedance network and second feedback impedance network comprise:

a capacitor; and

a variable resistance connected in parallel with the capacitor.

4. A receive equalizer circuit, comprising:

a first stage, comprising;

a first operational amplifier having a non-inverting input and an inverting input, and a non-inverting output and an inverting output;

a first input impedance network, coupled between a first input of the receive equalizer circuit and the inverting input of the first operational amplifier, and having an impedance selected from one of a first plurality of input impedance values; and

a first feedback impedance network coupled between the non-inverting output and the inverting input of the first operational amplifier, and having an impedance selected from one of a first plurality of feedback impedance values; and

a second stage, comprising;

a second operational amplifier, having an input, and an output;

a second input impedance network, coupled between the output of the first operational amplifier and the input of the second operational amplifier; and

a second feedback impedance network, coupled between the output and the input of the second operational amplifier;

a third input impedance network, coupled between a second input of the receive equalizer circuit and the noninverting input of the first operational amplifier, and having an impedance selected from one of a third plurality of input impedance values; and

a third feedback impedance network, coupled between the inverting output and the noninverting input of the first operational amplifier, and having an impedance selected from one of a third plurality of input impedance values.

5. The receive equalizer circuit of claim 4, wherein the second operational amplifier has a non-inverting input and an inverting input, and a non-inverting output and an inverting output;

wherein the inverting output of the first operational amplifier is coupled to the inverting input of the second operational amplifier through the second input impedance network;

wherein the second feedback impedance network is coupled between the non-inverting output and the inverting input of the second operational amplifier;

and further comprising;

a fourth input impedance network, coupled between a second input of the receive equalizer circuit and the noninverting input of the first operational amplifier; and

a fourth feedback impedance network, coupled between the inverting output and the noninverting input of the first operational amplifier.

6. The receive equalizer circuit of claim 5, wherein the fourth input impedance network has an impedance selected from one of a fourth plurality of input impedance values;

and wherein the second feedback impedance network has an impedance selected from one of a second plurality of feedback impedance values.

7. A receive equalizer circuit, comprising:

a first stage, comprising;

a first operational amplifier, having an input and an output;

a first input impedance network, coupled between an input of the receive equalizer circuit and the input of the first operational amplifier, and having an impedance selected from one of a first pluralitv of input impedance values; and

a first feedback impedance network, coupled between the output and the input of the first operational amplifier, and having an impedance selected from one of a first plurality of feedback impedance values; and

a second stage, comprising;

a second operational amplifier, having an input, and an output;

a second input impedance network, coupled between the output of the first operational amplifier and the input of the second operational amplifier; and

a second feedback impedance network, coupled between the output and the input of the second operational amplifier; and

a ladder filter, having a plurality of operational amplifier stages, and having an input coupled to the output of the first operational amplifier;

wherein the second stage serves as a first one of the plurality of operational amplifier stages of the ladder filter.

8. An analog front end circuit for a modem, integrated into a single integrated circuit, and comprising:

a digital interface, for communication of digital signals;

a digital-to-analog converter, coupled to the digital interface, for converting digital signals received from the digital interface into analog signals;

a transmit filter, for filtering the analog signals into a first transmit frequency band;

a receive equalizer for amplifymg the received analog signals according to a frequency response, comprising;

a first stage, comprising;

a first operational amplifier, having an input and an output;

a first input impedance network, for applying received analog signals, in a first receive frequency band, to the input of the first operational amplifier, and having an impedance selected from one of a first plurality of input impedance values; and

a first feedback impedance network, coupled between the output and the input of the first operational amplifier, and having an impedance selected from one of a first plurality of feedback impedance values; and

a second stage, comprising;

a second operational amplifier, having an input, and an output;

a second input impedance network, coupled between the output of the first operational amplifier and the input of the second operational amplifier; and

a second feedback impedance network, coupled between the output and the input of the second operational amplifier;

an analog-to-digital converter, coupled to the receive analog filter, for converting the filtered analog signals into digital signals; and

a receive digital filter, coupled to the analog-to-digital converter, for applying a digital filter function to the converted digital signals, and having an output coupled to the digital interface.

9. The analog front end circuit of claim 8, further comprising:

a receive analog filter, coupled to the output of the receive equalizer, for filtering analog signals amplified by the receive equalizer.

10. The analog front end circuit of claim 9, wherein the receive analog filter comprises a plurality of operational amplifier stages;

and wherein the second stage of the receive equalizer corresponds to a first one of the plurality of operational amplifier stages of the receive analog filter.

11. The analog front end circuit of claim 8, wherein each of the first input impedance network and first feedback impedance network comprise:

a capacitor; and

a variable resistance connected in parallel with the capacitor.

12. The analog front end circuit of claim 11, wherein each of the variable resistances comp rise a plurality of resistors connected in parallel with one another, each of the plurality of resistors being selectably enabled and disabled.

13. The analog front end circuit of claim 8, wherein the second input impedance network has an impedance selected from one of a second plurality of input impedance values;

and wherein the second feedback impedance network has an impedance selected from one of a second plurality of feedback impedance values.

14. The analog front end circuit of claim 8, wherein the analog signals are received on first and second differential inputs;

wherein the first operational amplifier has a non-inverting input and an inverting input, and a non-inverting output and an inverting output;

wherein the first differential input is coupled to the inverting input of the first operational amplifier through the first input impedance network;

wherein the first feedback impedance network is coupled between the non-inverting output and the inverting input of the first operational amplifier;

and further comprising;

a third input impedance network, coupled between the second differential input and the noninverting input of the first operational amplifier, and having an impedance selected from one of a third plurality of input impedance values; and

a third feedback impedance network, coupled between the inverting output and the noninverting input of the first operational amplifier, and having an impedance selected from one of a third plurality of input impedance values.

15. The analog front end circuit of claim 14, wherein the second operational amplifier has a non-inverting input and an inverting input, and a non-inverting output and an inverting output;

wherein the inverting output of the first operational amplifier is coupled to the inverting input of the second operational amplifier through the second input impedance network;

wherein the second feedback impedance network is coupled between the non-inverting output and the inverting input of the second operational amplifier;

and further comprising;

a fourth input impedance network, coupled between a second input of the receive equalizer circuit and the noninverting input of the first operational amplifier; and

a fourth feedback impedance network, coupled between the inverting output and the noninverting input of the first operational amplifier.

16. The analog front end circuit of claim 8, wherein the first receive frequency band includes frequencies higher than frequencies within the first transmit frequency band.

17. A digital subscriber line modem, comprising:

a host interface;

a digital transceiver function coupled to the host interface;

an analog line driver, for driving and receiving analog signals over a telephone facility; and

an analog front end circuit, integrated into a single integrated circuit, and comprising;

a digital interface, for communication of digital signals;

a digital-to-analog converter, coupled to the digital interface, for converting digital signals received from the digital interface into analog signals;

a transmit filter, for filtering the analog signals into a first transmit frequency band;

a receive equalizer for amplifying the received analog signals according to a frequency response, comprising;

a first stage, comprising;

a first operational amplifier, having an input and an output;

a first input impedance network, for applying received analog signals, in a first receive frequency band, to the input of the first operational amplifier, and having an impedance selected from one of a first plurality of input impedance values; and

a first feedback impedance network, coupled between the output and the input of the first operational amplifier, and having an impedance selected from one of a first plurality of feedback impedance values; and

a second stage, comprising;

a second operational amplifier, having an input, and an output;

a second input impedance network, coupled between the output of the first operational amplifier and the input of the second operational amplifier; and

a second feedback impedance network, coupled between the output and the input of the second operational amplifier;

an analog-to-digital converter, coupled to the receive analog filter, for converting the filtered analog signals into digital signals; and

a receive digital filter, coupled to the analog-to-digital converter, for applying a digital filter function to the converted digital signals, and having an output coupled to the digital interface.

18. The modem of claim 17, wherein the digital transceiver function comprises a programmable digital signal processor.

19. The modem of claim 17, wherein the first receive frequency band includes frequencies higher than frequencies within the first transmit frequency band.

20. The modem of claim 17, further comprising:

a receive analog filter, coupled to the output of the receive equalizer, for filtering analog signals amplified by the receive equalizer.

21. The modem of claim 20, wherein the receive analog filter comprises a plurality of operational amplifier stages;

and wherein the second stage of the receive equalizer corresponds to a first one of the plurality of operational amplifier stages of the receive analog filter.

22. The modem of claim 17, wherein each of the first input impedance network and first feedback impedance network comprise:

a capacitor; and

a variable resistance connected in parallel with the capacitor.

23. The modem of claim 22, wherein each of the variable resistances comprise a plurality of resistors connected in parallel with one another, each of the plurality of resistors being selectably enabled and disabled.

24. The modem of claim 17, wherein the second input impedance network has an impedance selected from one of a second plurality of input impedance values;

and wherein the second feedback impedance network has an impedance selected from one of a second plurality of feedback impedance values.

25. The modem of claim 17, wherein the analog signals are received on first and second differential inputs;

wherein the first operational amplifier has a non-inverting input and an inverting input, and a non-inverting output and an inverting output;

wherein the first differential input is coupled to the inverting input of the first operational amplifier through the first input impedance network;

wherein the first feedback impedance network is coupled between the non-inverting output and the inverting input of the first operational amplifier;

and further comprising;

a third input impedance network, coupled between the second differential input and the noninverting input of the first operational amplifier, and having an impedance selected from one of a third plurality of input impedance values; and

a third feedback impedance network, coupled between the inverting output and the noninverting input of the first operational amplifier, and having an impedance selected from one of a third plurality of input impedance values.

26. The modem of claim 17, wherein the second operational amplifier has a non-inverting input and an inverting input, and a non-inverting output and an inverting output;

wherein the inverting output of the first operational amplifier is coupled to the inverting input of the second operational amplifier through the second input impedance network;

wherein the second feedback impedance network is coupled between the non-inverting output and the inverting input of the second operational amplifier;

and further comprising;

a fourth input impedance network, coupled between a second input of the receive equalizer circuit and the noninverting input of the first operational amplifier; and

a fourth feedback impedance network, coupled between the inverting output and the noninverting input of the first operational amplifier.

27. The modem of claim 17, wherein the first receive frequency band includes frequencies higher than frequencies within the first transmit frequency band.