Technique for minimizing decision feedback equalizer wordlength in the presence of a DC component

• US 6,226,323 B1
• Filed: 11/03/1999
• Issued: 05/01/2001
• Est. Priority Date: 11/03/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hung, Hing "Ada" T., Tan, Loke Kun, Liu, Tian-Min
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US09/433,731
• Time in Patent Office: 545 Days
• Field of Search: 375/232, 375/233, 375/346, 375/348, 375/350, 708/322, 708/323
• US Class Current: 375/233
• CPC Class Codes: H04B 1/68 for wholly or partially suppressing the carrier or one side band
• CPC Class Codes: H04L 2025/03382 Single of vestigal sideband
• CPC Class Codes: H04L 2025/0342 QAM
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2027/0032 at baseband and passband
• CPC Class Codes: H04L 2027/0042 the equaliser providing the offset correction per se
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 2027/0087 Out-of-band signals, (e.g. pilots)
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/066 Carrier recovery circuits H04L27/2271 takes precedence
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 27/3427 in which the constellation is the n - fold Cartesian product of a single underlying two-dimensional constellation
• CPC Class Codes: H04L 27/3827 in which the carrier is recovered using only the demodulated baseband signals
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/211 Ghost signal cancellation H04N23/81 takes precedence
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27

Abstract

A system for reducing the complexity of an adaptive decision feedback equalizer, for use in connection with a dual-mode QAM/VSB receiver system is disclosed. QAM and VSB symbols, which are expressed in two'"'"'s compliment notation, include an extra bit required to compensate for a fixed offset term introduced by the two'"'"'s compliment numbering system. A decision feedback equalizer includes a decision feedback filter section which operates on symbolic decisions represented by a wordlength which excludes the added bit representing the offset. The vestigal word is convolved with the decision feedback filter'"'"'s coefficients, while a DC component, corresponding to the excluded bit, is convolved with the same coefficient values in a correction filter. The two values are summed to provide an ISI compensation signal at the input of a decision device such as a slicer. A DC component representing a pilot tone in VSB transmission systems also introduces a DC component, and additional bits, to a VSB wordlength. These additional bits are similarly excluded and the vestigal representation convolved with coefficient values in a decision feedback filter. The DC component, including the pilot tone representation, is convolved with the same coefficient values in a correction filter.

Claims

1. An integrated circuit receiver, including an adaptive decision feedback equalizer, comprising:

a feedforward filter;

a decision circuit;

a decision feedback filter coupled in parallel fashion with the decision circuit; and

an offset generation circuit, wherein the offset generation circuit receives coefficient values from the decision feedback filter and provides an offset signal to an output signal from the decision feedback filter, the offset signal corresponding to a bitwise representation of a DC component.

2. The integrated circuit receiver according to claim 1, further comprising:

a complex input signal corresponding to a multi-level constellation of symbols, each symbol represented by a number of bits; and

wherein the number of bits representing each symbol is determined by a power of two which identifies a size of the constellation.

3. The integrated circuit receiver according to claim 2, wherein the bit representation of the constellation includes a fixed offset term.

4. The integrated circuit receiver according to claim 3, wherein the fixed offset term is capable of representation by adding an additional bit to each number bits representing a symbol.

5. The integrated circuit receiver according to claim 4, wherein the offset signal corresponds to a digital value determined by the additional bit.

6. The integrated circuit receiver according to claim 5, wherein the constellation is a 256-QAM constellation and the number of bits representing each symbol is four, the offset signal corresponding to a −

½

bit offset in the representation of QAM signals.

7. An integrated circuit receiver operating on a constellation of complex symbols, each symbol represented by a number N of bits, the receiver comprising:

an adaptive decision feedback equalizer including;

a decision feedback filter, constructed to receive a symbol decision having a wordlength of N−

1 bits, the decision feedback filter outputting a compensated symbol decision having a wordlength of N−

1 bits;

an offset generation circuit, generating a DC value corresponding to an Nth bit representation; and

a summing circuit for combining the decision feedback filter output and the DC value generated by the offset generation circuit.

8. The integrated circuit receiver according to claim 7, wherein the offset generation circuit is a filter.

9. The integrated circuit receiver according to claim 8, further comprising:

a feedforward filter; and

a decision circuit, coupled in parallel fashion with the decision feedback filter, the decision circuit outputting an N−

1 bit wide word representing symbol decisions and a symbol error term.

10. The integrated circuit receiver according to claim 9, wherein the symbol error term adaptively trains filter coefficients of the decision feedback filter, the decision feedback filter coefficients provided to the offset generation circuit.

11. An integrated circuit receiver operating on a constellation of complex symbols, each symbol capable of representation by a digital word having a wordlength N of bits, the receiver comprising:

a feedback filter, constructed to receive an input stimulus signal having a wordlength of N−

1 bits, the feedback filter outputting an output signal having a wordlength of N−

1 bits;

a correction filter constructed to provide an output signal having a single bit representation, wherein the correction filter receives coefficients from the feedback filter that are processed to generate the single-bit output signal; and

means for combining the feedback filter output and the correction filter output to define a signal having a value consistent with an N-bit representation.

12. The integrated circuit receiver according to claim 11, wherein the correction filter outputs a signal corresponding to a fixed offset term introduced by a representation of complex symbols in a first numbering system.

13. The integrated circuit receiver according to claim 11, wherein the correction filter outputs a signal corresponding to a fixed offset term introduced by a pilot tone inserted into a transmitted spectrum.

14. The integrated circuit receiver according to claim 11, wherein the correction filter outputs a signal corresponding to a fixed offset term representing the sum of a fixed offset introduced by a representation of complex symbols in a first numbering system and a fixed offset introduced by a pilot tone inserted into a transmitted spectrum.

15. The integrated circuit receiver according to claim 11, further comprising:

a feedforward filter; and

a decision device, coupled in parallel fashion with the feedback filter, the decision device outputting symbolic decisions in an N−

1 bit representation and further outputting a symbolic error term associated with each decision.

16. The integrated circuit receiver according to claim 15, wherein the symbolic error term adaptively trains filter coefficients of the feedback filter, the feedback filter providing an ISI compensation to symbolic decisions expressed in an N−

1 bit representation.

17. The integrated circuit receiver according to claim 16, wherein the correction filter receives filter coefficients from the feedback filter, the correction filter providing an ISI compensation to a fixed offset term.

18. The integrated circuit receiver according to claim 17, the constellation comprising a 256-QAM constellation, each real and each imaginary symbol represented by a 5-bit word in two'"'"'s compliment notation, the 5-bit word comprising a 4-bit portion expressing each symbol'"'"'s relative position within the constellation and a 1-bit portion expressing a fixed offset between each symbol'"'"'s relative position and its absolute position within the constellation.

19. In an integrated circuit receiver, a method for adaptively equalizing symbols expressed as a digital word, the method comprising:

identifying a nibble component of the word, the nibble component representing a fixed offset value;

truncating the word to a vestigal representation excluding the nibble component;

convolving the vestigal representation with coefficient taps in a first filter;

convolving the fixed offset value, corresponding to the excluded nibble component, with coefficient taps in a second filter, wherein the coefficient taps are received from the first filter; and

summing the convolutions.

20. The method according to claim 19, wherein the first filter is a decision feedback filter.

21. The method according to claim 20, wherein the second filter is a DC correction filter.