Multi-pair transceiver decoder system with low computation slicer

• US 6,226,332 B1
• Filed: 08/09/1999
• Issued: 05/01/2001
• Est. Priority Date: 11/13/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kruse, David, Hatamian, Mehdi, Agazzi, Oscar E., Abnous, Arthur
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): GHAYOUR, MOHAMMAD H
• Application Number:
  US09/370,353
• Time in Patent Office: 631 Days
• Field of Search: 375/288, 375/260, 375/262, 375/265, 375/229, 375/230, 375/232, 375/233, 714/792, 714/794, 714/795, 714/796, 714/797
• US Class Current: 375/288
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318502 Test of Combinational circuits
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03369 Partial response
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03496 as a prediction filter
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 2025/03745 Timing of adaptation
• CPC Class Codes: H04L 25/03038 : with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 : with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03267 : with decision feedback equalisers
• CPC Class Codes: H04L 25/03885 : adaptive
• CPC Class Codes: H04L 25/067 : providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 25/14 : Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 25/497 : by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 7/0062 : detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 : Processing of samples having at least three levels, e.g. soft decisions

Abstract

A method and a system for decoding information signals encoded by a multi-state encoding architecture and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are detected in a symbol decoder, implemented using look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The symbol decoder is implemented as a pair of slicers, each detecting an input signal with respect to one of two disjoint symbol-subsets. A third slicer detects the input with respect to the union of the two disjoint symbol-subsets. Decisions from the first, second and third slicers are processed to define 1D square error terms expressed in Hamming metrics. Reduced bit count error terms allow follow-on error processing to be performed with a minimum of computational complexity. The 1D errors are combined to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.

Claims

1. A symbol decoder included in a receiver configured to receive information encoded in accordance with a multi-level symbolic scheme and over a multi-dimensional transmission channel, the symbol decoder comprising:

an input, coupled to receive an input signal;

a first slicer, coupled to detect the input signal with respect to a first one of two disjoint one-dimensional symbol-subsets; and

a second slicer, coupled to detect the input signal with respect to a second one of the two disjoint one-dimensional symbol-subsets;

wherein the first slicer outputs a first decision term and a first error term with respect to the first one of the two disjoint one-dimensional symbol-subsets, the second slicer outputting a second decision term and a second error term with respect to the second one of the two disjoint one-dimensional symbol-subsets; and

wherein each of the first and second error terms is expressed by a digital representation having substantially fewer bits than the input signal.

2. The symbol decoder according to claim 1, wherein each of the first and second error terms represents a distance metric between the input signal and a symbol in the respective one of the two disjoint one-dimensional symbol-subsets.

3. The symbol decoder according to claim 2, wherein each of the first and second decision terms represents a symbol in the respective one of the two disjoint one-dimensional symbol-subsets.

4. The symbol decoder according to claim 1, wherein each of the first and second error terms is expressed by a digital representation having fewer than four bits.

5. The symbol decoder according to claim 1, wherein each of the first and second error terms is expressed by a digital representation having fewer than three bits.

6. The symbol decoder according to claim 3, wherein the multi-dimensional transmission channel has L dimensions and wherein the first and second error terms are 1-dimensional error terms, the 1-dimensional error terms being combined to generate a set of L-dimensional error terms such that each of the L-dimensional error terms represents a distance between a received L-dimensional word and a nearest codeword.

7. A symbol decoder included in a receiver configured to receive information encoded in accordance with a multi-level symbolic scheme and over a multi-dimensional transmission channel, the symbol decoder comprising:

an input to receive an input signal;

a first slicer coupled to the input, the first slicer detecting the input signal with respect to a first one of two disjoint one-dimensional symbol-subsets;

a second slicer coupled to the input, the second slicer detecting the input signal with respect to a second one of the two disjoint one-dimensional symbol-subsets; and

a third slicer coupled to detect the input signal with respect to a union set of the two disjoint one-dimensional symbol-subsets.

8. The symbol decoder according to claim 7,

wherein the first slicer outputs a first decision with respect to the first one of the two disjoint one-dimensional symbol-subsets;

wherein the second slicer ouputs a second decision with respect to the second one of the two disjoint one-dimensional symbol-subsets; and

wherein the third slicer outputs a third decision with respect to the union set of the two disjoint one-dimensional symbol-subsets.

9. The symbol decoder according to claim 8 further comprising:

a first combination logic block configured to combine the first decision with the third decision, the first combination logic block defining a first error term; and

a second combination logic block configured to combine the second decision with the third decision, the second combination logic block defining a second error term.

10. The symbol decoder according to claim 9 further comprising:

a first square error generation block configured to operate on the first error term so as to define a square error representation thereof; and

a second square error generation block configured to operate on the second error term so as to define a square error representation thereof.

11. The symbol decoder according to claim 10, wherein each of the first and second combination logic blocks is implemented using a look-up table, the combination operation and error term definition being performed by consulting an appropriate entry in the look-up table.

12. The symbol decoder according to claim 11, wherein each the first and second square error generation blocks is implemented using a look-up table, the square error definition being performed by consulting an appropriate entry in the look-up table.

13. The symbol decoder according to claim 11, wherein the look-up table is implemented in a read-only-memory storage device.

14. The symbol decoder according to claim 11, wherein the look-up table is implemented as a random logic integrated circuit.

15. The symbol decoder according to claim 11, wherein the look-up table is implemented as a programmable-logic-array integrated circuit.

16. The symbol decoder according to claim 11, wherein each of the error terms is expressed as a digital representation having one bit.

17. A method for symbol decoding in a receiver configured to receive information encoded in accordance with a multi-level symbolic scheme and over a multi-dimensional transmission channel, the method comprising:

providing an input for receiving an input signal;

detecting the input signal with respect to a first one of two disjoint one-dimensional symbol-subsets in a first slicer;

detecting the input signal with respect to a second one of the two disjoint one-dimensional symbol-subsets in a second slicer; and

detecting the input signal with respect to a union set of the two disjoint one-dimensional symbol-subsets in a third slicer.

18. The method according to claim 17, further comprising:

producing from the first slicer a first decision with respect to the first one of the two disjoint one-dimensional symbol-subsets;

producing from the second slicer a second decision with respect to the second one of the two disjoint one-dimensional symbol-subsets; and

producing from the third slicer a third decision with respect to the union set of the two disjoint symbol-subsets.

19. The method according to claim 18, further comprising:

combining the first decision with the third decision in a first combination block so as to define a first error term; and

combining the second decision with the third decision in a second combination block so as to define a second error term.

20. The method according to claim 19, further comprising:

operating on the first error term so as to define a square error representation thereof in a first square error block; and

operating on the second error term so as to define a square error representation thereof in a second square error block.

21. The method according to claim 20, wherein each of the first and second combination blocks is implemented using a look-up table, the combination operation and error term definition being performed by consulting an appropriate entry in the look-up table.

22. The method according to claim 21, wherein each of the first and second square error blocks is implemented using a look-up table, the square error definition being performed by consulting an appropriate entry in the look-up table.

23. The method according to claim 21, wherein the look-up table is implemented in a read-only-memory storage device.

24. The method according to claim 21, wherein the look-up table is implemented as a random logic integrated circuit.

25. The method according to claim 21, wherein the look-up table is implemented as a programmable-logic-array integrated circuit.

26. The method according to claim 21, wherein each of the first and second error terms is expressed as a digital representation having one bit.