Apparatus with failure recovery and method therefore

• US 6,226,556 B1
• Filed: 07/09/1998
• Issued: 05/01/2001
• Est. Priority Date: 07/09/1998
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Itkin, Yuval, Baruch, Ezra
• Primary Examiner(s): Grant, William
• Assistant Examiner(s): RODRIGUEZ, PAUL L
• Application Number:
  US09/112,533
• Time in Patent Office: 1,027 Days
• Field of Search: 700/21, 700/4, 700/2, 700/3, 700/82, 700/293, 700/297, 714/10, 714/23, 714/24, 713/340, 713/330, 713/322
• US Class Current: 700/21
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations
• CPC Class Codes: H02J 9/061 for DC powered loads

Abstract

A radio (20) having a power supply (24); a power reservoir (25); a plurality of processors (22, 36), having inner registers which store a first flag indicating whether a power failure occurred; a plurality of memory banks (28, 38), coupled to the plurality of processors (22, 36); a power failure sensor (26), coupled to the power supply (24) and to the plurality of processors (22, 36); a power on reset unit (34), coupled to the power failure sensor (26); a clock generator (32), and a power failure recovery controller (30′), coupled to the power supply (24), the energy reservoir (25), the power failure sensor (26), the clock generator (32), the plurality of processors (22, 36) and to the power on reset unit (34). When a short power failure occurs, the power reservoir (25) supplies energy to the radio (20), the power failure recovery controller (30) notifies the plurality of processors (22, 36) that a power failure has occurred, and the plurality of processors (22, 36) write their status to the plurality of memories (28, 38), enter a predetermined state and notify the power failure recovery controller (30) that they enter the predetermined state. After receiving these signals, the power failure recovery controller disables the clock generator, until the power failure ends.

Claims

1. An apparatus comprising:

a power supply;

an energy reservoir, coupled to the power supply, for receiving energy from the power supply and for supplying voltage when a power failure occurs;

a processor, coupled to the power supply and to the energy reservoir;

wherein as a result of power failures the processor enters a predetermined mode;

a memory, coupled to the processor, for storing a status of the processor;

a power failure sensor, coupled to the power supply, for sensing when the supply voltage is below or above a first level;

a power failure recovery controller, coupled to the power supply, the energy reservoir, the power failure sensor, and to the processor;

wherein the power failure recovery controller notifies the processor when the supply voltage is below the first level and when the supply voltage raises above the first level, wherein after the processor enters a predetermined state, the power failure recovery controller reduces power consumption of the apparatus;

a plurality of further processors and a plurality of further memories; and

wherein each processor is coupled to one of the memories, for storing and reading the processor statuses; and

a clock generator, coupled to the power failure recover controller, to the plurality of processors, and to the plurality of memories, wherein most of all of the plurality of processors and memories are built from cells, wherein a cell average power dissipation P is proportional to the cell operating frequency F by the power of k, k>

0, and wherein the power failure recovery controller reduces the power consumption of the apparatus by disabling the clock generator.

2. The apparatus of claim 1 further comprising a power on reset unit, coupled to the power failure sensor, for resetting the plurality of processors when the supply voltage, which was below a second level, raised above the second level;

and wherein the power failure sensor can sense the supply voltage is below a first level and below a second level.

3. The apparatus of claim 2 wherein when the power failure sensor senses that the supply voltages is below the first level, it sends a first signal to the power failure recovery controller;

wherein when the power failure sensor senses that the supply voltage, which was previously below the first level, raises above the first level, it sends a second signal to the power failure recovery controller;

wherein when the power failure sensor senses that the supply voltage is below the second level, it sends a third signal to the power on reset unit; and

wherein when the power failure sensor senses that the supply voltage which was previously below the second level, raises above the second level, it sends a fourth signal to the power on reset unit.

4. The apparatus of claim 3 wherein when the power failure recovery controller receives the first signal, the power failure recovery controller sends a ‘

CLOSE’

signal to the processor;

wherein, as a result of the ‘

CLOSE’

signal the processor writes to the memory its current state, sets a first flag in its register, sends the power failure recovery controller a ‘

STOP’

signal, indicating that it entered a predetermined status;

wherein after the power failure recovery controller receives the ‘

STOP’

signal it sends ‘

DISABLE’

signal which disables the clock generator; and

wherein when the power failure recovery controller receives the second signal the power failure recovery controller sends an ‘

ENABLE’

signal which enables the clock generator.

5. The apparatus of claim 1 wherein the cells are CMOS cells.

6. An apparatus comprising:

a power supply;

an energy reservoir, coupled to the power supply, for receiving energy from the power supply and for supplying voltage when a power failure occurs;

a first processor, coupled to the power supply and to the energy reservoir;

wherein as a result of power failures the first processor enters a predetermined mode;

a memory, coupled to the first processor, for storing a status of the first processor;

a power failure sensor, coupled to the power supply, for sensing when the supply voltage is below or above a first level; and

a power failure recovery controller, coupled to the power supply, the energy reservoir, the power failure sensor, and to the first processor;

wherein the power failure recovery controller notifies the first processor when the supply voltage is below the first level and when the supply voltage raises above the first level, wherein after the first processor enters a predetermined state, the power failure recovery controller reduces power consumption of the apparatus;

wherein the first processor can activate a second processor, after receiving an indication that the supply voltage is below the first level.

7. The apparatus of claim 6 wherein when the supply voltage is below the first level, the power failure recovery controller sends a ‘

CLOSE’

signals to all the processors simultaneously;

wherein power failure recovery controller checks the status of the second processor, in a periodical manner, and sends it ‘

CLOSE’

signals until the second processor enters a predetermined status.

8. An apparatus comprising:

a power supply;

an energy reservoir, coupled to the power supply, for receiving energy from the power supply and for supplying voltage when a power failure occurs;

a processor, coupled to the power supply and to the energy reservoir;

wherein as a result of power failures the processor enters a predetermined mode;

a memory, coupled to the processor, for storing a status of the processor;

a power failure sensor, coupled to the power supply, for sensing when the supply voltage is below or above a first level; and

a power failure recovery controller, coupled to the power supply, the energy reservoir, the power failure sensor, and to the processor;

wherein the power failure recovery controller notifies the processor when the supply voltage is below the first level and when the supply voltage raises above the first level, wherein after the processor enter a predetermined state, the power failure recovery controller reduces power consumption of the apparatus; and

a low frequency clock generator, which is activated during the power failure;

a counter, coupled to the low frequency clock generator, and to the power failure recovery controller;

wherein the counter is reset at the beginning of the power failure;

wherein the low frequency clock generator causes the counter to increment, so that the counter measures the length of the power failure;

a register, coupled to the counter and to the processor, for storing the content of the counter and wherein the processors can read the register.

9. The apparatus of claim 8, wherein the apparatus communicates with a base radio station, wherein the base station and the apparatus each have a timing unit, wherein the timing units need to be synchronized;

and wherein after the occurrence of a power failure, the timing unit of the apparatus is updated, according to the register content.

10. A method for operating an apparatus having a processor, a power reservoir, and a power failure recovery controller, comprising the steps of:

sensing if a supply voltage provided by the power reservoir is below a first level;

if ‘

YES’

, storing a status of the processor;

notifying the power failure recovery controller that the status was stored and entering a predetermined mode;

reducing power consumption of the apparatus;

sensing if one or more of the supply voltages is above a first level;

if ‘

YES’

, ending the reduction in power consumption of the apparatus;

reading the status of the processor from a memory;

wherein as long as the supply voltage is below the first level, substantially sending power from the power reservoir

wherein if the supply voltage is below a first level;

sending a ‘

CLOSE’

signal to the processor and a further processor;

checking if a ‘

STOP’

signal arrived;

if a ‘

STOP’

signal did not arrive, checking if the voltage supply is still under the first level and if ‘

NO’

go to initialization step, if ‘

YES’

reducing the power consumption of the apparatus;

if a ‘

STOP’

signal did arrive, reducing the power consumption of the apparatus;

sensing if the supply voltage that was below a first level is above the first level; and

if ‘

YES’

ending the reduction of power consumption.

11. A method for operating an apparatus having a first processor and a second processor, a power reservoir, and a power failure recovery controller, comprising the steps of:

initializing the apparatus;

sensing if a supply voltage provided by the power reservoir is below a first level;

if ‘

YES’

, storing a status of the first processor and the second processor;

notifying the power failure recovery controller that the status of the first processor was stored and entering a predetermined mode;

checking if the second processor has entered the predetermined mode;

if ‘

YES’

disabling a clock generator;

if ‘

NO’

sending ‘

CLOSE’

signals to the second processor until the second processor sends a ‘

STOP’

signal;

reducing energy consumption of the apparatus;

sensing if the supply voltage that was below a first level is above the first level;

if ‘

YES’

ending the reduction of energy consumption;

wherein the length of a power failure is measured by a counter; and

wherein the processor can read the content of the counter.

12. The method of claim 11 wherein the apparatus communicates with a base radio station;

wherein the base station and the apparatus each have a timing unit;

wherein the timing units need to be synchronized; and

wherein after the occurrence of a power failure, the timing unit of the apparatus is updated, according to the content of the counter.

13. The method of claim 11 wherein after sensing that the supply voltage is below a first level, sending a ‘

CLOSE’

signal to the first processor and the second processor;

checking if a ‘

STOP’

signal arrived from the first processor;

if a ‘

STOP’

signal did not arrive, checking if the supply voltage is still under the first level and if ‘

YES’

sending a ‘

CLOSE’

signal to the first processor and the second processor;

if ‘

NO’

go to initialization step;

if a ‘

STOP’

signal did arrive, resetting the ‘

CLOSE’

signal sent to the first processor and the second processor;

checking if a ‘

STOP’

signal arrived from the second processor;

if a ‘

STOP’

signal did not arrive, checking if the voltage supply is still under the first level and if ‘

YES’

sending a ‘

CLOSE’

signal to the second processor;

if ‘

NO’

go to initialization step;

reducing power consumption of the apparatus;

sensing if the supply voltage that was below a first level is above the first level; and

if ‘

YES’

ending the reduction of power consumption.