Integrated circuit memory devices including internal stress voltage generating circuits and methods for built-in self test (BIST)

• US 6,226,764 B1
• Filed: 09/16/1998
• Issued: 05/01/2001
• Est. Priority Date: 01/16/1998
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Cheol-ha
• Primary Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US09/154,060
• Time in Patent Office: 958 Days
• Field of Search: 714/718, 714/721, 714/733, 365/201, 365/185.11, 365/185.23, 365/194, 365/196, 365/230.03, 365/230.06
• US Class Current: 714/718
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

Integrated circuit memory devices include a stress voltage generator that generates a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and that applies the stress voltage to the memory cell array during the stress BIST of the memory cell array. The stress voltage generator is preferably responsive to a BIST request signal and to a stress test signal that are applied from external of the integrated circuit memory device, to apply the stress voltage to the memory cell array and to perform a BIST of the memory cell array. The stress voltage generator is responsive to the BIST request signal and absence of the stress test signal, to apply the internal supply voltage to the memory cell array and to perform a BIST of the memory cell array. Accordingly, circuits within the integrated circuit memory device can be responsive to external test signals to generate stress voltages during BIST.

Claims

1. An integrated circuit memory device comprising:

a memory cell array in the integrated circuit memory device; and

a stress voltage generator in the integrated circuit memory device that generates a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and that applies the stress voltage to the memory cell array during stress built-in self test of the memory cell array;

wherein the stress voltage generator is responsive to a built-in self test request signal and to a stress test signal that are applied from external of the integrated circuit memory device, to apply the stress voltage to the memory cell array and to perform a built-in self test of the memory cell array, and is responsive to the built-in test request signal and absence of the stress test signal, to apply the internal supply voltage to the memory cell array and to perform the built-in self test of the memory cell array.

2. An integrated circuit memory device according to claim 1 further comprising:

a stress controller that is responsive to the stress test signal that is applied from external of the integrated circuit memory device, to control the stress voltage generator; and

a BIST unit that is responsive to the built-in self test request signal that is applied from external of the integrated circuit memory device to perform the built-in self test of the memory cell array.

3. An integrated circuit memory device comprising:

a memory cell array in the integrated circuit memory device; and

a stress voltage generator in the integrated circuit memory device that generates a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and that applies the stress voltage to the memory cell array during stress built-in self test of the memory cell array;

wherein the stress voltage generator comprises;

an internal supply voltage generator that generates the stress voltage from a reference voltage; and

a clamping unit that clamps the stress voltage to the internal supply voltage in response to a control signal.

4. An integrated circuit memory device according to claim 3 further comprising:

a stress controller that is responsive to the stress test signal that is applied from external of the integrated circuit memory device, to disable the control signal.

5. An integrated circuit memory device comprising:

a memory cell array in the integrated circuit memory device; and

a stress voltage generator in the integrated circuit memory device that generates a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and that applies the stress voltage to the memory cell array during stress built-in self test of the memory cell array;

wherein the stress voltage generator clamps the stress voltage to the internal supply voltage of the integrated circuit and applies the clamped stress voltage to the memory cell array during normal built-in self test of the memory cell array.

6. An integrated circuit memory device comprising:

a memory cell array in the integrated circuit memory device; and

means, in the integrated circuit memory device, for generating a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and for applying the stress voltage to the memory cell array during stress built-in self test of the memory cell array;

wherein the generating means is responsive to a built-in self test request signal and to a stress test signal that are applied from external of the integrated circuit memory device, for applying the stress voltage to the memory cell array and for performing a built-in self test of the memory cell array, and is responsive to the built-in test request signal and absence of the stress test signal, for applying the internal supply voltage to the memory cell array and for performing the built-in self test of the memory cell array.

7. An integrated circuit memory device comprising:

a memory cell array in the integrated circuit memory device; and

means, in the integrated circuit memory device, for generating a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and for applying the stress voltage to the memory cell array during stress built-in self test of the memory cell array;

wherein the generating means comprises;

means for generating the stress voltage from a reference voltage; and

means for clamping the stress voltage to the internal supply voltage in response to a control signal.

8. An integrated circuit memory device according to claim 7 further comprising:

means for deactivating the control signal in response to the stress test signal that is applied from external of the integrated circuit memory device.

9. An integrated circuit memory device comprising:

a memory cell array in the integrated circuit memory device; and

means, in the integrated circuit memory device, for generating a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and for applying the stress voltage to the memory cell array during stress built-in self test of the memory cell array;

wherein the generating means further comprises means for clamping the stress voltage to the internal supply voltage of the integrated circuit and for applying the clamped stress voltage to the memory cell array during normal built-in self test of the memory cell array.

10. A method of stress built-in self testing a memory cell array in an integrated circuit memory device, comprising the following steps which are performed in the integrated circuit memory device:

generating, in the integrated circuit memory device, a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device;

applying the stress voltage to the memory cell array; and

simultaneously with the applying step, performing stress built-in self testing of the memory cell array;

wherein the generating step comprises the steps of;

generating the stress voltage from a reference voltage; and

clamping the stress voltage to the internal supply voltage in response to a control signal.

11. A method of testing a memory cell array in an integrated circuit memory device, comprising the following steps which are performed in the integrated circuit memory device in response to an external signal:

determining whether the integrated circuit memory device is in normal Built-In Self Test (BIST) mode or in stress BIST mode in response to the external signal;

performing BIST on the memory cell array using an internal supply voltage if the memory is in normal BIST mode;

generating a stress voltage that is higher than the internal supply voltage and performing BIST on the memory cell array using the stress voltage if the memory is in stress BIST mode;

determining whether the integrated circuit memory device is in externally controlled test mode in response to the external signal; and

testing the memory cell array under external control if the integrated circuit memory device is in the externally controlled test mode.

12. A method according to claim 11 wherein the generating step comprises the steps of:

generating the stress voltage from a reference voltage; and

clamping the stress voltage to the internal supply voltage in response to a control signal.

13. A method according to claim 11 wherein the step of determining whether the integrated circuit memory device is in the externally controlled test mode in response to the external signal comprises the step of determining whether the integrated circuit memory device is in an externally controlled normal test mode or in an externally controlled direct access test mode in response to the external signal.

14. A method according to claim 13 wherein the step of testing the memory cell array under external control if the integrated circuit memory device is in externally controlled test mode comprises the steps of:

testing the memory cell array normally if the integrated circuit memory device is in the externally controlled normal test mode; and

directly accessing and testing the memory cell array if the integrated circuit memory device is in the externally controlled direct access test mode.

15. An integrated circuit memory device, comprising:

a memory cell array;

means for determining whether the integrated circuit memory device is in normal Built-In Self Test (BIST) mode or in stress BIST mode in response to an external signal that is applied to the integrated circuit memory device;

means for performing BIST on the memory cell array using an internal supply voltage if the memory is in normal BIST mode;

means for generating a stress voltage that is higher than the internal supply voltage and for performing BIST on the memory cell array using the stress voltage if the memory is in stress BIST mode;

means for determining whether the integrated circuit memory device is in externally controlled test mode in response to the external signal; and

means for testing the memory cell array under external control if the integrated circuit memory device is in the externally controlled test mode.

16. An integrated circuit memory device according to claim 15 wherein the generating means comprises:

means for generating the stress voltage from a reference voltage; and

means for clamping the stress voltage to the internal supply voltage in response to a control signal.

17. An integrated circuit memory device according to claim 15 wherein the means for determining whether the integrated circuit memory device is in the externally controlled test mode in response to the external signal comprises means for determining whether the integrated circuit memory device is in an externally controlled normal test mode or in an externally controlled direct access test mode in response to the external signal.

18. An integrated circuit memory device according to claim 17 wherein the means for testing the memory cell array under external control if the integrated circuit memory device is in externally controlled test mode comprises:

means for testing the memory cell array normally if the integrated circuit memory device is in the externally controlled normal test mode; and

means for directly accessing and testing the memory cell array if the integrated circuit memory device is in the externally controlled direct access test mode.