Event based test system data memory compression

• US 6,226,765 B1
• Filed: 02/26/1999
• Issued: 05/01/2001
• Est. Priority Date: 02/26/1999
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Le, Anthony, Turnquist, James Alan
• Primary Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US09/259,402
• Time in Patent Office: 795 Days
• Field of Search: 714/724, 714/718, 714/32, 714/33, 714/39, 714/735, 714/736, 714/738, 714/741, 714/742, 365/189.07, 365/201, 324/73.1, 702/79, 702/85
• US Class Current: 714/718
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer

Abstract

An event based test system for storing event data in a compressed form to reduce the size of a memory and decompressing the data to produce the events for testing a device under test (DUT). The event based test system includes a clock count memory for storing clock count data of each event wherein the clock count data is formed of one or more data words depending on the value of the integral part data, a vernier data memory for storing vernier data of each event wherein the vernier data memory stores vernier data for two or more events in the same memory location, an address sequencer for generating address data for accessing the clock count memory and the vernier data memory, a decompressor for reproducing the clock count data from the clock count memory and the vernier data from the vernier data memory corresponding to each event. The event based test system may further include an event process controller for producing an overall delay time of each event relative to a predetermined reference point based on the clock count data and vernier data from the decompressor, and a fine delay controller for generating each event based on the overall delay time to produce test signals for testing the DUT.

Claims

1. An event based test system for testing an electronics device under test (DUT), comprising:

a clock count memory for storing clock count data of each event which is an integer multiple of a reference clock period (integral part data), said clock count data being formed of one or more data words depending on the value of the integral part data, and at least one data word including a flag to indicate whether the next word being needed, a number of vernier data attached to a current event, and at least a part of the integral part data;

a vernier data memory for storing vernier data of each event which is a fraction of the reference clock period (fractional part data), said vernier data memory storing vernier data for two or more events in the same memory location;

an address sequencer for generating address data for accessing said clock count memory and said vernier data memory to read out said clock count data and said vernier data therefrom; and

a decompressor for reproducing the clock count data from the clock count memory and the vernier data from the vernier data memory corresponding to each event.

2. An event based test system as defined in claim 1, further comprising:

an event process controller for producing an overall delay time of each event relative to a predetermined reference point based on the clock count data and vernier data from the decompressor; and

a fine delay controller for generating each event based on said overall delay time to produce test signals for testing the DUT.

3. An event based test system as defined in claim 1, wherein a timing of each event is a time difference between two adjacent events and is defined by the clock count data and the vernier data.

4. An event based test system as defined in claim 1, wherein the decompressor is comprised of:

a counter for loading the clock count data from the clock count memory and down counting the clock count data by the reference clock;

a clock count state machine for interpreting the clock count data and controlling the operation of the counter in loading the clock count data and counting the reference clock;

a storage and selection circuit for storing the vernier data from the vernier data memory for two or more events in a parallel manner and selecting the vernier data to send the vernier data in a series manner to the event process controller; and

a vernier control state machine for controlling the operation of the storage and selection circuit based on instructions received from the clock count state machine.

5. An event based test system as defined in claim 4, wherein the storage and selection circuit includes a pair of registers for storing the vernier data from the vernier data memory in a parallel fashion, and a multiplexer for selecting the vernier data from one of the registers.

6. An event based test system as defined in claim 5, wherein the storage and selection circuit includes:

a first and second registers for storing the vernier data from the vernier data memory in a parallel fashion;

a third register for receiving the vernier data from the first register;

a fourth register for receiving the vernier data from the second register;

a first multiplexer for receiving a plurality of vernier data in a parallel form from the first and third registers and producing the vernier data in a series form based on the control of the vernier control state machine;

a second multiplexer for receiving a plurality of vernier data in a parallel form from the second and fourth registers and producing the vernier data in a series form based on the control of the vernier control state machine; and

a third multiplexer for selecting an output of the first multiplexer or the second multiplexer second based on the control of the vernier control state machine.

7. An event based test system as defined in claim 1, further comprising a pin electronics between said fine delay controller and said DUT.

8. An event based test system as defined in claim 1, wherein said data word is comprised of eight (8) bits and at least one bit of which is used as the flag, and the clock count data stored in the clock count memory is comprised of a varying number of data words ranging from one word to four words in which the first data word includes data indicating the number of vernier data attached to the current event.