Method and apparatus for generating error detection data for encapsulated frames

• US 6,226,771 B1
• Filed: 12/14/1998
• Issued: 05/01/2001
• Est. Priority Date: 12/14/1998
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Masterson, Timothy F., Edwards, James M., Jennings, William E., Hilla, Stephen C.
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US09/211,682
• Time in Patent Office: 869 Days
• Field of Search: 714/758, 714/757, 714/776, 714/781, 714/784, 714/807, 714/752, 714/52
• US Class Current: 714/758
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0061 Error detection codes

Abstract

An error detection generator calculates error detection data for insertion into encapsulated frames. The error detection generator is configured to calculate multiple error detection values and insert them into corresponding fields of the encapsulated frames. The error detection generator includes a controller, three cyclic redundancy check (CRC) engines and at least one multiplexer. Each CRC engine is selectively enabled by the controller to calculate a frame check sequence (FCS) value on a different portion of the frame. Downstream CRC engines also receive the outputs from the upstream CRC engines so that these earlier FCS values may be used during subsequent calculations. The outputs of the CRC engines are also inserted into the appropriate fields of the encapsulated frames by the multiplexer.

Claims

1. An error detection generator for calculating two or more error detection values or insertion into an encapsulated frame having a plurality of fields, the error detection generator comprising:

a first, a second and a third cyclic redundancy check (CRC) engine each configured to receive the encapsulated frame and having means for calculating an error detection value;

an output multiplexer configured to receive the encapsulated frame and coupled to each of the CRC engines for inserting the calculated error detection values into respective fields of the encapsulated frame; and

a controller operably coupled to the CRC engines and the output multiplexer, the controller selectively enabling and disabling the CRC engines to calculate corresponding error detection values based on different fields of the encapsulated frame and setting the output multiplexer to insert the calculated error detection values into the respective fields of the encapsulated frame.

2. The error detection generator of claim 1 wherein the CRC engines are arranged in a first, second and third streamwise fashion so that a first error detection value calculated by the first CRC engine is selectively available to the second and third CRC engines and a second error detection value calculated by the second CRC engine is selectively available to the third CRC engine.

3. The error detection generator of claim 2 wherein the controller selectively provides the second CRC engine with either the encapsulated frame or the first error detection value and selectively provides the third CRC engine with either the encapsulated frame, the first error detection value or the second error detection value.

4. The error detection generator of claim 3 further comprising:

a first CRC multiplexer associated with the second CRC engine; and

a second CRC multiplexer associated with the third CRC engine,

wherein the controller is configured to set the first CRC multiplexer so as to provide the second CRC engine with either the encapsulated frame or the first error detection value and to set the second CRC multiplexer so as to provide the third CRC engine with either the encapsulated frame, the first error detection value or the second error detection value.

5. The error detection generator of claim 4 wherein the controller is configured to examine the contents of a given field of the encapsulated frame to determine whether error detection values are to be inserted into the respective encapsulated frame.

6. The error detection generator of claim 5 wherein the controller is further configured to determine the number of error detection values to be inserted in an encapsulated frame based on the contents of the given field of the respective encapsulated frame.

7. The error detection generator of claim 6 further comprising first and second flip circuits associated with the first CRC engine, the first flip circuit selectively transposing the bit ordering of a portion of the encapsulated frame received at the first CRC engine and the second flip circuit selectively transposing the bit ordering of the error detection value calculated by the first CRC engine.

8. The error detection generator of claim 7 wherein the controller activates and de-activates the two flip circuits in response to one or more fields of the encapsulated frame.

9. The error detection generator of claim 8 wherein the encapsulated frame includes an Ethernet frame and the error detection generator calculates and inserts two error detection values in the encapsulated frame.

10. The error detection generator of claim 8 wherein the encapsulated frame includes a Token Ring frame and the error detection generator calculates and inserts three error detection values in the encapsulated frame.

11. A network switch comprising:

Interswitch Link (ISL) circuitry for encapsulating one or more local area network (LAN) frames having a plurality of fields within at least one ISL header; and

an error detection generator for calculating two or more error detection values for insertion into the ISL-encapsulated frames, the error detection generator comprising;

three cyclic redundancy check (CRC) engines each configured to receive the ISL-encapsulated frame and having means for calculating an error detection value;

an output multiplexer configured to receive the ISL-encapsulated frame and coupled to each of the CRC engines for inserting the calculated error detection values into respective fields of the encapsulated frames; and

a controller operably coupled to the CRC engines and the output multiplexer, the controller selectively enabling and disabling the CRC engines to calculate corresponding error detection values based on different fields of the ISL-encapsulated frames and setting the output multiplexer to insert the calculated error detection values into the respective fields of the ISL-encapsulated frames.

12. A method for calculating and inserting error detection values into encapsulated frames, the method comprising the steps of:

determining the number of error detection values to be calculated for a given encapsulated frame;

selectively enabling a first cyclic redundancy check (CRC) engine, in response to the step of determining, to calculate a first error detection value based on the given encapsulated frame;

enabling a second CRC engine to calculate a second error detection value based on a first portion of the given encapsulated frame;

enabling a third CRC engine to calculate a third error detection value based on a second portion of the given encapsulated frame; and

inserting the error detection values calculated by the first, second and third CRC engines into pre-defined fields of the given encapsulated frame.

13. The method of claim 12 further comprising the steps of:

providing the error detection value calculated by the first CRC engine to the second and third CRC engines for use in their respective error detection calculations; and

providing the error detection value calculated by the second CRC engine to the third CRC engine for use in its respective error detection calculation.

14. The method of claim 12 wherein, in response to determining that two error detection values are to be calculated for the given encapsulated frame, the first CRC engine is not enabled.

15. An error detection generator for calculating two or more error detection values for insertion into an encapsulated frame having a plurality of fields, the error detection generator comprising:

a plurality of cyclic redundancy check (CRC) engines each configured to receive the encapsulated frame and having means for calculating an error detection value;

an output multiplexer configured to receive the encapsulated frame and coupled to each of the CRC engines for inserting the calculated error detection values into respective fields of the encapsulated frame;

first and second flip circuits associated with a first CRC engine, the first flip circuit selectively transposing the bit ordering of a portion of the encapsulated frame received at the first CRC engine and the second flip circuit selectively transposing the bit ordering of the error detection value calculated by the first CRC engine; and

a controller operably coupled to the CRC engines, the output multiplexer and the two flip circuits, the controller selectively enabling and disabling the CRC engines to calculate corresponding error detection values based on different fields of the encapsulated frame, activating the two flip circuits, in response to the bit ordering of the encapsulated frame, and setting the output multiplexer to insert the calculated error detection values into the respective fields of the encapsulated frame.