Modifying a design layer of an integrated circuit using overlying and underlying design layers

• US 6,226,781 B1
• Filed: 08/12/1998
• Issued: 05/01/2001
• Est. Priority Date: 08/12/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hause, Frederick N., Nistler, John L., Etter, Phillip J.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Garbowski, Leigh Marie
• Application Number:
  US09/132,980
• Time in Patent Office: 993 Days
• Field of Search: 716/11, 716/17, 716/18, 716/19, 716/20, 716/21, 716/1, 716/2, 430/5, 430/1, 378/34
• US Class Current: 716/52
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 7/70441 Optical proximity correction [OPC]
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A computer-implemented method is provided in which a design layer of an integrated circuit is altered by spatial definition using underlying and overlying design layers. That is, the specific layers of an integrated circuit that impact the layer being modified are taken into account. According to an embodiment, the computer-implemented method is performed using, e.g., a CAD program. First, an original layout design comprising a plurality of design layers representing respective levels of an integrated circuit is generated. The targeted properties, e.g., electrical properties, of features in one design layer are determined based upon the arrangement of features in other design layers relative to the features in that one design layer. The features in the design layer being modified are then separated into different working layers such that each working layer includes features having at least one common targeted property. The features in each working layer may then be separately modified based upon the mutual targeted property of that working layer.

Claims

1. A computer-implemented method for performing a proximity correction on an integrated circuit layout design, comprising:

generating an original layout design comprising a plurality of design layers representing respective levels of an integrated circuit;

determining targeted properties of first features in one design layer, wherein the targeted properties depend upon an arrangement of second features in other design layers relative to the first features;

separating the first features of the first design layer into different working layers, wherein each working layer comprises the first features that share a mutual targeted property; and

separately altering the first features in said each working layer based upon the mutual targeted property of that working layer.

2. The method of claim 1, wherein the targeted properties comprise electrical properties.

3. The method of claim 1, wherein said separately altering the first features comprises applying a different algorithm to said each working layer.

4. The method of claim 1, wherein said separately altering the first features comprises using a different set of functions to vary dimensions of the first features in said each working layer.

5. The method of claim 1, further comprising verifying that the features within said each working layer meet pre-defined parameters using a design rule checker.

6. The method of claim 1, further comprising merging the working layers into a corrected layout design subsequent to said separately altering the first features.

7. The method of claim 1, further comprising transferring the corrected layout design to a reticle for use in lithography.

8. The method of claim 1, wherein the first features represent local interconnects, and wherein the second features represent active areas and polysilicon structures.

9. The method of claim 8, wherein said separating the first features of the first design layer into different working layers comprises placing a first portion of the first features into a first working layer, wherein the first portion represents the local interconnects that comprise a minimum area and overlap the active areas.

10. The method of claim 9, wherein said separating the first features of the first design layer into different working layers further comprises placing a second portion of the first features into a second working layer, wherein the second portion represents the local interconnects that comprise the minimum area and overlap the polysilicon structures.

11. The method of claim 10, wherein said separating the first features of the first design layer into different working layers further comprises placing a third portion of the first features into a third working layer, wherein the third portion represents the local interconnects that comprise areas greater than the minimum area and overlap the polysilicon structures.

12. The method of claim 11, wherein said separating the first features of the first design layer into different working layers further comprises placing a fourth portion of the first features into a fourth working layer, wherein the fourth portion represents the local interconnects that comprise the areas greater than the minimum area and overlap the active areas.

13. A computer-implemented method for performing a proximity correction on an integrated circuit layout design, comprising:

generating an original layout design comprising a plurality of design layers representing respective levels of an integrated circuit;

determining a targeted electrical property of a first feature in one design layer, wherein the targeted electrical property depends upon a position of the first feature relative to a second feature in another design layer;

attributing the first feature to a working layer comprising other features having the same targeted electrical property as the first feature; and

altering the first feature and the other features in the working layer based upon the targeted electrical property.

14. The method of claim 13, wherein said altering the first features and the other features comprises applying an algorithm to the working layer.

15. The method of claim 13, wherein said altering the first features and the other features comprises varying dimensions of the first feature and the other feature.

16. The method of claim 13, further comprising verifying that the first feature and the other features meet pre-defined parameters using a design rule checker.

17. The method of claim 13, further comprising placing the working layer into a corrected layout design subsequent to said altering the first feature and the other features.

18. The method of claim 13, further comprising transferring the corrected layout design to a reticle for use in lithography.