Method of manufacturing fuse element used in memory device and fuse element

• US 6,228,690 B1
• Filed: 08/25/1999
• Issued: 05/08/2001
• Est. Priority Date: 08/27/1998
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: NEC Corporation
• Inventors: Mikuni, Yasunori
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Brewster, William M.
• Application Number:
  US09/382,514
• Time in Patent Office: 622 Days
• Field of Search: 438/132, 438/281, 438/467, 438/601, 148/55, 257/529
• US Class Current: 438/132
• CPC Class Codes: H01L 23/5258 the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a fuse element used in a semiconductor memory device by which P/W repair rate can be improved, and a fuse element produced by such method. The method comprises: forming a first interlayer insulating film including BPSG so as to cover the fuse line and planarizing the top surface; forming a polysilicon film on the first interlayer insulating film; forming a second interlayer insulating film including BPSG on the polysilicon film and planarizing the top surface; partially etching the second interlayer insulating film and an upper region of the polysilicon film to form a first opening portion above the fuse line; forming a wiring layer on inner walls of the first opening portion and on the second interlayer insulating film; partially etching the wiring layer and the polysilicon film at the bottom portion of the first opening portion to form a second opening portion above the fuse line and to expose the first interlayer insulating film; forming an insulating film on at least inner walls of the first second opening portions; and partially etching the insulating film at the bottom portion of the second opening portion and an upper region of the first interlayer insulating film to form a third opening portion above the fuse line.

Claims

1. A method of manufacturing a fuse element used in a memory device comprising:

preparing a substrate on which a grounding layer is formed;

forming a fuse line on said grounding layer formed on said substrate;

forming a first interlayer insulating film including BPSG on said grounding layer so as to cover said fuse line;

planarizing the top surface of said first interlayer insulating film;

forming a polycrystalline silicon (polysilicon) film on said first interlayer insulating film planarized;

forming a second interlayer insulating film including BPSG on said polysilicon film;

planarizing the top surface of said second interlayer insulating film;

partially etching said second interlayer insulating film and an upper region of said polysilicon film to form a first opening portion above said fuse line, wherein said polysilicon film is exposed within said first opening portion;

forming a metal wiring layer on side and bottom walls of said first opening portion and on said second interlayer insulating film;

partially etching said metal wiring layer and said polysilicon film at the bottom portion of said first opening portion to form a second opening portion within said first opening portion and above said fuse line, wherein said first interlayer insulating film is exposed within said second opening portion;

forming an insulating film portion on at least inner walls of said first opening portion and said second opening portion; and

partially etching at the bottom portion of said second opening portion said insulating film portion and an upper region of said first interlayer insulating film to form a third opening portion within said second opening portion and above said fuse line, wherein said first interlayer insulating film is exposed in said third opening portion.

2. A method of manufacturing a fuse element used in a memory device as set forth in claim 1, wherein said insulating film portion comprises at least one layer of interlayer insulating film and a cover insulating film.

3. A method of manufacturing a fuse element used in a memory device as set forth in claim 1, wherein said planarizing the top surface of said first interlayer insulating film is performed by reflow processing said first interlayer insulating film and then performing CMP processing on said first interlayer insulating film.

4. A method of manufacturing a fuse element used in a memory device as set forth in claim 3, wherein when said first interlayer insulating film is reflow processed, said first interlayer insulating film is heated in nitrogen atmosphere at a temperature between 780 degrees Celsius and 820 degrees Celsius.

5. A method of manufacturing a fuse element used in a memory device as set forth in claim 1, wherein said planarizing the top surface of said second interlayer insulating film is performed by reflow processing said second interlayer insulating film and then performing CMP processing on said second interlayer insulating film.

6. A method of manufacturing a fuse element used in a memory device as set forth in claim 5, wherein when said second interlayer insulating film is reflow processed, said second interlayer insulating film is heated in nitrogen atmosphere at a temperature between 780 degrees Celsius and 820 degrees Celsius.

7. A method of manufacturing a fuse element used in a memory device as set forth in claim 1, wherein when said first opening portion is formed, said polysilicon layer functions as an etching stopper by utilizing a difference between the etching rate of said second interlayer insulating film and the etching rate of said polysilicon film.

8. A method of manufacturing a fuse element used in a memory device as set forth in claim 1, wherein when said first opening portion is formed, an etching process is used in which the etching rate of said polysilicon film is smaller than the etching rate of said second interlayer insulating film.

9. A method of manufacturing a fuse element used in a memory device as set forth in claim 1, wherein when partially etching said metal wiring layer and said polysilicon film at the bottom portion of said first opening portion to form said second opening portion, said polysilicon film within said second opening portion is completely removed by controlling the quantity of overetching of said polysilicon film.

10. A method of manufacturing a fuse element used in a memory device as set forth in claim 1, wherein, when forming said third opening portion, the thickness of the layers remaining on said fuse line is adjusted by controlling etching condition of partially etching the insulating film portion and the upper region of said first interlayer insulating film at the bottom portion of said second opening portion.

11. A method of manufacturing a fuse element used in a memory device as set forth in claim 1, wherein said memory device is a dynamic random acces memory (DRAM) device.